公开(公告)号：US20250028660A1

公开(公告)日：2025-01-23

申请号：US18452554

申请日：2023-08-20

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F13/16 ,  G06F1/10 ,  G06F3/06 ,  G06F13/28 ,  G06F13/40 ,  G11C5/04 ,  G11C7/10 ,  G11C7/20 ,  G11C8/12 ,  G11C8/18 ,  G11C16/00 ,  G11C29/02 ,  G11C29/04

Abstract: A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit is mounted on the module board and coupled between a respective set of data signal lines and a respective set of memory devices. Each respective buffer circuit is configured to receive the module control signals and the module clock signal, and to buffer a respective set of data signals in response to the module control signals and the module clock signal. Each respective buffer circuit includes a delay circuit configured to adjust the timing of at least one of the respective set of data signals by an amount based on at least one module control signal in a previous operation.

公开(公告)号：US12061562B2

公开(公告)日：2024-08-13

申请号：US18000125

申请日：2021-06-01

Applicant: Netlist Inc.

Inventor： Jordan Horwich ,  Jerry Alston ,  Chih-Cheh Chen ,  Patrick Lee ,  Scott Milton ,  Jeekyoung Park

IPC: G06F12/0815 ,  G06F12/0862 ,  G06F12/0891 ,  G06F13/16

CPC classification number: G06F13/1673 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0891 ,  G06F13/1642

Abstract: A memory expansion device operable with a host computer system (host) comprises a non-volatile memory (NVM) subsystem, cache memory, and control logic configurable to receive a submission from the host including a read command and specifying a payload in the NVM subsystem and demand data in the payload. The control logic is configured to request ownership of a set of cache lines corresponding to the payload, to indicate completion of the submission after acquiring ownership of the cache lines, and to load the payload to the cache memory. The set of cache lines correspond to a set of cache lines in a coherent destination memory space accessible by the host. The control logic is further configured to, after indicating completion of the submission and in response to a request from the host to read demand data in the payload, return the demand data after determining that the demand data is in the cache memory.

公开(公告)号：US11994982B2

公开(公告)日：2024-05-28

申请号：US17202021

申请日：2021-03-15

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G11C8/12 ,  G06F12/00 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06

CPC classification number: G06F12/00 ,  G11C5/025 ,  G11C5/04 ,  G11C5/066 ,  G11C8/12

Abstract: A memory module comprises dynamic random access memory (DRAM) devices arranged in ranks, and a module controller configurable to receive address and control signals for a memory operation, and to output first module control signals to the DRAM devices, causing a selected rank to output or receive N-bit-wide data. The module controller is further configurable to output second module control signals to a plurality of data buffers coupled to the DRAM devices via module data lines. Each respective data buffer includes a n-bit-wide (n

公开(公告)号：US20240119002A1

公开(公告)日：2024-04-11

申请号：US18468712

申请日：2023-09-17

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Junkil RYU

IPC: G06F12/0813 ,  G06F9/455 ,  G06F12/02 ,  G06F12/1045 ,  G06F12/109 ,  G06F13/00 ,  H04L65/40

CPC classification number: G06F12/0813 ,  G06F9/455 ,  G06F12/0284 ,  G06F12/1054 ,  G06F12/109 ,  G06F13/00 ,  H04L65/40 ,  G06F2212/1044

Abstract: A node in a network including a plurality of nodes comprises persistent memory; non-persistent memory, a node control device operatively coupled to the persistent memory and the non-persistent memory, a local interface for interfacing with the local server in the UMA node, and a network interface for interfacing with other nodes. The node control device is configured to translate between a local unified memory access (UMA) address space accessible by applications running on a local server and a global UMA address space that is mapped to a physical UMA address space. The physical UMA address space includes physical address spaces associated with different UMA nodes in the cluster of UMA nodes. Thus, a server in the UMA network can access the physical address spaces at other UMA nodes without going through the servers in the other UMA nodes.

公开(公告)号：US11914481B2

公开(公告)日：2024-02-27

申请号：US18154500

申请日：2023-01-13

Applicant: Netlist, Inc.

Inventor： Scott H. Milton ,  Jeffrey C. Solomon ,  Kenneth S. Post

IPC: G06F11/00 ,  G06F11/14 ,  G06F11/07 ,  G11C16/34 ,  G11C29/42 ,  G11C29/44 ,  G11C29/04

CPC classification number: G06F11/1458 ,  G06F11/073 ,  G06F11/076 ,  G06F11/0793 ,  G11C16/349 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A system and method for configuring fault tolerance in nonvolatile memory (NVM) are operative to set a first threshold value, declare one or more portions of NVM invalid based on an error criterion, track the number of declared invalid NVM portions, determine if the tracked number exceeds the first threshold value, and if the tracked number exceeds the first threshold value, perform one or more remediation actions, such as issue a warning or prevent backup of volatile memory data in a hybrid memory system. In the event of backup failure, an extent of the backup can still be assessed by determining the amount of erased NVM that has remained erased after the backup, or by comparing a predicted backup end point with an actual endpoint.

公开(公告)号：US11862267B2

公开(公告)日：2024-01-02

申请号：US16286246

申请日：2019-02-26

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Soonju Choi

IPC: G11C29/10 ,  G11C29/12 ,  G11C5/04

CPC classification number: G11C29/10 ,  G11C29/12 ,  G11C5/04

Abstract: A memory module is operable in a computer system to communicate data with a system memory controller via a system memory bus. The memory module comprises a plurality of memory devices mounted on a circuit board, a data module mounted on the circuit board and coupled between the plurality of memory devices and the system memory bus, and a control circuit mounted on the circuit board and coupled to the data module, the plurality of memory devices, and the system memory bus. The data module includes a plurality of data handlers in a plurality of integrated circuits. The memory module is operable in any of a plurality of modes, including a first mode and a second mode. The plurality of memory devices in the first mode is accessed by the system memory controller for normal memory read or write operations. The plurality of memory devices in the second mode communicate data signals with the data module while the memory module is not being accessed by the system memory controller for normal memory read or write operations.

公开(公告)号：US20230418712A1

公开(公告)日：2023-12-28

申请号：US18154500

申请日：2023-01-13

Applicant: Netlist, Inc.

Inventor： Scott H. MILTON ,  Jeffrey C. SOLOMON ,  Kenneth S. POST

IPC: G06F11/14 ,  G06F11/07 ,  G11C16/34 ,  G11C29/42 ,  G11C29/44

CPC classification number: G06F11/1458 ,  G06F11/0793 ,  G06F11/073 ,  G06F11/076 ,  G11C16/349 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C2029/0409

Abstract: A system and method for configuring fault tolerance in nonvolatile memory (NVM) are operative to set a first threshold value, declare one or more portions of NVM invalid based on an error criterion, track the number of declared invalid NVM portions, determine if the tracked number exceeds the first threshold value, and if the tracked number exceeds the first threshold value, perform one or more remediation actions, such as issue a warning or prevent backup of volatile memory data in a hybrid memory system. In the event of backup failure, an extent of the backup can still be assessed by determining the amount of erased NVM that has remained erased after the backup, or by comparing a predicted backup end point with an actual endpoint.

公开(公告)号：US11762788B2

公开(公告)日：2023-09-19

申请号：US17114478

申请日：2020-12-07

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F3/00 ,  G06F12/00 ,  G06F13/00 ,  G06F13/16 ,  G06F1/10 ,  G06F3/06 ,  G06F13/28 ,  G06F13/40 ,  G11C5/04 ,  G11C7/10 ,  G11C8/18 ,  G11C16/00 ,  G11C29/02 ,  G11C7/20 ,  G11C8/12 ,  G11C29/04

CPC classification number: G06F13/1673 ,  G06F1/10 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F13/1642 ,  G06F13/28 ,  G06F13/4027 ,  G11C5/04 ,  G11C7/1006 ,  G11C7/1066 ,  G11C7/1093 ,  G11C8/18 ,  G11C16/00 ,  G11C29/023 ,  G11C29/028 ,  H05K999/99 ,  G11C7/109 ,  G11C7/20 ,  G11C8/12 ,  G11C2029/0407

Abstract: A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit is mounted on the module board and coupled between a respective set of data signal lines and a respective set of memory devices. Each respective buffer circuit is configured to receive the module control signals and the module clock signal, and to buffer a respective set of data signals in response to the module control signals and the module clock signal. Each respective buffer circuit includes a delay circuit configured to delay the respective set of data signals by an amount determined based on at least one of the module control signals.

公开(公告)号：US11561715B2

公开(公告)日：2023-01-24

申请号：US16950731

申请日：2020-11-17

Applicant: Netlist, Inc.

Inventor： Hyun Lee

IPC: G06F3/06 ,  G06F13/10 ,  G06F12/02 ,  G06F13/28 ,  G06F12/06 ,  G06F12/0868

Abstract: A memory module comprises a volatile memory subsystem, a non-volatile memory subsystem, and a module controller coupled to the volatile memory subsystem and to the non-volatile memory subsystem. The module controller is configurable to control data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller includes a data selection circuit configurable to pre-search data transferred from the non-volatile memory with respect to one or more search criteria before providing the pre-select data relevant to the one or more search criteria to the volatile memory subsystem.

公开(公告)号：US20230010660A1

公开(公告)日：2023-01-12

申请号：US17660446

申请日：2022-04-25

Applicant: Netlist, Inc.

Inventor： Hyun LEE

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0868 ,  G06F12/0815

Abstract: A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the non-volatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals. The NV controller and the non-volatile memory can be mounted on the motherboard.