公开(公告)号：US20250123905A1

公开(公告)日：2025-04-17

申请号：US18488867

申请日：2023-10-17

Applicant: NVIDIA Corp.

Inventor： Sana Damani ,  Peter Nelson

IPC: G06F9/52 ,  G06T1/20 ,  G06T1/60

Abstract: A process to ameliorate scoreboard aliasing in multi-threaded data processors whereby, in response to executing at least one long-latency instruction in a first thread, a shared hardware scoreboard is incremented. A shared software register is incremented and the shared software register is spilled to a first per-thread register, and execution is switched to a second thread. After execution switches back to the first thread, execution of the first thread is suspended until the shared hardware scoreboard reaches a value at or below a difference between a value in the shared software register and the value spilled into the first per-thread register.

公开(公告)号：US20250103076A1

公开(公告)日：2025-03-27

申请号：US18894507

申请日：2024-09-24

Applicant: NVIDIA Corp.

Inventor： Siddharth Saxena ,  Sudhir Shrikantha Kudva ,  Miguel Rodriguez ,  Vijay Srinivasan ,  Tezaswi Raja ,  Tom Gray ,  Santosh Santosh

IPC: G05F1/56 ,  G04F10/00 ,  H03M7/16

Abstract: Reference voltage generators including a header circuit configured to pass current from a power supply to a time-to-digital converter, an amount of the current to pass determined by a thermometer code, and logic to update the thermometer code based on a comparison between an output of the time-to-digital converter and a digital code representing a reference voltage level.

公开(公告)号：US20250004275A1

公开(公告)日：2025-01-02

申请号：US18744378

申请日：2024-06-14

Applicant: NVIDIA Corp.

Inventor： Jonghyun Kim ,  Ward Lopes ,  David Luebke

IPC: G02B27/01 ,  G02B27/28 ,  G03H1/22 ,  G06T19/00

Abstract: Optical systems including an interferometer utilizing a spatial light modulator. A light guide including a first beam splitter and multiple mirrors directs incoherent light through the beam splitter to the interferometer to generate an interference light pattern, and further directs the interference light pattern back to the first beam splitter via the mirrors.

公开(公告)号：US20240385381A1

公开(公告)日：2024-11-21

申请号：US18318132

申请日：2023-05-16

Applicant: NVIDIA Corp.

Inventor： Angad Rekhi ,  Benjamin Giles Lee

IPC: G02B6/293 ,  G02B6/12

Abstract: Optical transceiver architecture utilizing micro-ring modulators and micro-ring resonators configured to route resonant wavelengths of light injected into each micro-ring resonator's input port and through port to that micro-ring resonator's drop port and add port, respectively. The micro-ring resonators drop two distinct streams of data modulated onto the same optical wavelength, or two wavelengths separated by an integer number of free spectral ranges coupled into the micro-ring resonators in two different directions.

公开(公告)号：US12135607B2

公开(公告)日：2024-11-05

申请号：US18186464

申请日：2023-03-20

Applicant: NVIDIA Corp.

Inventor： Gautam Bhatia ,  Sunil Sudhakaran ,  Kyutaeg Oh

IPC: G06F11/10 ,  G06F11/07

Abstract: Data bits are encoded in one or both of an eleven bit seven pulse amplitude modulated three-level (PAM-3) symbol (11b7s) format and a three bit two symbol (3b2s) format on a plurality of data channels and on an error correction channel. One or more of a cyclic redundancy check (CRC) value, a poison value, and a severity value are encoded as 11b7s and/or 3b2s PAM-3 symbols on the error correction channel.

公开(公告)号：US11997306B2

公开(公告)日：2024-05-28

申请号：US18184524

申请日：2023-03-15

Applicant: NVIDIA Corp.

Inventor： Johan Pontus Andersson ,  Jim Nilsson ,  Tomas Guy Akenine-Möller

IPC: H04N19/132 ,  G06T15/06 ,  H04N19/182 ,  H04N19/423 ,  H04N19/513

CPC classification number: H04N19/513 ,  G06T15/06 ,  H04N19/132 ,  H04N19/182 ,  H04N19/423

Abstract: A method dynamically selects one of a first sampling order and a second sampling order for a ray trace of pixels in a tile where the selection is based on a motion vector for the tile. The sampling order may be a bowtie pattern or an hourglass pattern.

公开(公告)号：US11973501B2

公开(公告)日：2024-04-30

申请号：US17730352

申请日：2022-04-27

Applicant: NVIDIA Corp.

Inventor： Jiwang Lee ,  Jaewon Lee ,  Hsuche Nee ,  Po-Chien Chiang ,  Wen-Hung Lo ,  Michael Ivan Halfen ,  Abhishek Dhir

IPC: H03K19/1776 ,  H03K19/17736 ,  H03K19/17784

CPC classification number: H03K19/1776 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17784

Abstract: A multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (IO) channel and a unified receiver coupled to a second end of the shared IO channel. The unified receiver is coupled to apply a preconfigured analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is switched to the shared IO channel.

公开(公告)号：US20240094291A1

公开(公告)日：2024-03-21

申请号：US17932808

申请日：2022-09-16

Applicant: NVIDIA Corp.

Inventor： Mahmut Yilmaz ,  Vinod Pagalone ,  Munish Aggarwal ,  Doochul Shin

IPC: G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/318536 ,  G01R31/31727 ,  G01R31/318597

Abstract: A circuit for improving control over asynchronous signal crossings during circuit scan tests includes multiple scan registers and a decoder configured to translate a combined output of the scan registers into multiple one-hot controls to the local clock gates of scan registers disposed in multiple different clock domains. Programmable registers are provided to selectively enable and disable the local clock gates of the different clock domains.

公开(公告)号：US20240030916A1

公开(公告)日：2024-01-25

申请号：US17932052

申请日：2022-09-14

Applicant: NVIDIA Corp.

Inventor： Walker Joseph Turner ,  John Poulton ,  Sanquan Song

IPC: H03K19/0185 ,  H03K19/00

CPC classification number: H03K19/018521 ,  H03K19/0013 ,  H03K3/356165

Abstract: A level-shifting circuits utilizing storage cells for shifting signals low-to-high or high-to-low include control drivers with moving supply voltages. The moving supply voltages may power positive or negative supply terminals of the control drivers. The control drivers drive gates of common-source configured devices coupled to storage nodes of the storage cell.

公开(公告)号：US20240013033A1

公开(公告)日：2024-01-11

申请号：US18163603

申请日：2023-02-02

Applicant: NVIDIA Corp.

Inventor： Haoyu Yang ,  Haoxing Ren

IPC: G06N3/0464 ,  G03F1/36

CPC classification number: G06N3/0464 ,  G03F1/36

Abstract: A circuit mask optimizer utilizes a Convolutional Fourier Neural Operator (CFNO) to efficiently learn layout tile dependencies, enabling stitch-less largescale mask optimization with limited intervention of legacy tools. Litho-guided self training via a trained machine learning model provides non-convex optimization, enabling iterative model and dataset refinements at a substantial performance improvement over conventional solutions.