公开(公告)号：US20250070768A1

公开(公告)日：2025-02-27

申请号：US18938128

申请日：2024-11-05

Applicant: PARADE TECHNOLOGIES, LTD.

Inventor： YingFan LEE ,  Zhih-Ling LU ,  Andrew LEE ,  Xin JIN

IPC: H03K5/156

Abstract: A method controls the duty cycle distortion of clock signals. An electronic device obtains an input clock signal and generates a first output voltage and a second output voltage from the input clock signal. The first output voltage has a first direct current (DC) voltage level indicating, in real time, a first duty cycle length of high voltage duty cycles of the input clock signal. The second output voltage has a second DC voltage level indicating, in real time, a second duty cycle length of low voltage duty cycles of the input clock signal. The difference between the first and second DC voltage levels corresponds to the duty cycle distortion level of the input clock signal. A duty cycle control signal is generated based on the difference between the first and second DC voltage levels to control the high voltage duty cycles of the input clock signal.

公开(公告)号：US12222611B2

公开(公告)日：2025-02-11

申请号：US18182268

申请日：2023-03-10

Applicant: PARADE TECHNOLOGIES, LTD

Inventor： You Ben Yin ,  Quan Yu ,  Yueh-Lin Yang

IPC: G02F1/1345 ,  G02F1/1333 ,  G06F3/041 ,  G06F3/044

Abstract: An electronic device has a display substrate including a display area, a driver area, and a fan-out area. The fan-out area is divided to a plurality of fan-out regions, and has interconnects configured to access display elements formed on the display area. The driver area is adjacent to the fan-out area and configured to receive a driver chip having a plurality of pads. The interconnects of the fan-out area include a subset of first interconnects. Each first interconnect passes a first fan-out region and a second fan-out region to access a respective display element. A first portion of the subset of first interconnects is formed on the first fan-out region with a first interconnect pitch, and a second portion of the subset of first interconnects is formed on the second fan-out region with a second interconnect pitch different from the first interconnect pitch.

公开(公告)号：US12206409B2

公开(公告)日：2025-01-21

申请号：US18182996

申请日：2023-03-13

Applicant: PARADE TECHNOLOGIES, LTD

Inventor： Chieh-Yuan Chao ,  Jenghung Tsai

IPC: H03K19/173 ,  H03K17/693 ,  H03K19/003 ,  H03K19/1776

Abstract: An electronic device includes two multiplexer branches, a modulation circuit, and an output interface coupled to the modulation circuit and two multiplexer branches. A first multiplexer branch generate s first output signal from a first selection signal, a first inverse signal, and a first input signal. The first inverse signal is substantially complementary to the first selection signal. A second multiplexer branch generates a second output signal from the first selection signal, the first inverse signal, and a second input signal. The modulation circuit generates a logic output signal from the first input signal and the second input signal, independently of the first selection signal and the first inverse signal. The output interface generates a multiplexed signal tracking one of the first input signal and the second input signal based on the first output signal, the second output signal, and the logic output signal.

公开(公告)号：US20240348419A1

公开(公告)日：2024-10-17

申请号：US18301152

申请日：2023-04-14

Applicant: PARADE TECHNOLOGIES, LTD

Inventor： Canruo Ying ,  Yi-Han Cheng

IPC: H04L7/00

CPC classification number: H04L7/0087

Abstract: This application is directed to controlling bandwidths of clock recovery circuit in an electronic device. The electronic device includes a clock recovery circuit and a bandwidth controller coupled to the clock recovery circuit. The clock recovery circuit is configured to receive a data signal carrying a stream of data bits according to a reference clock frequency and recover a clock signal from the data signal. The bandwidth controller is configured to control the clock recovery circuit to start with a pull-in bandwidth, settle at a target bandwidth, and apply an intermediate bandwidth between the pull-in bandwidth and target bandwidth. The intermediate bandwidth is greater than the target bandwidth and less than the pull-in bandwidth. In some implementations, the bandwidth controller controls the clock recovery circuit to apply one or more additional bandwidths to the clock signal after the pull-in bandwidth and the intermediate bandwidth and before the target bandwidth.

公开(公告)号：US11676974B2

公开(公告)日：2023-06-13

申请号：US17488263

申请日：2021-09-28

Applicant: PARADE TECHNOLOGIES, LTD.

Inventor： Yueh-Lin Yang ,  Haijun Chen ,  Tatao Hsu ,  Jonathan Huang

IPC: H01L27/12 ,  G02F1/1345

CPC classification number: H01L27/124 ,  G02F1/13452 ,  G02F1/13456 ,  G02F1/13458

Abstract: An electronic device has a display substrate including a display area, a driver area, and a fan-out area. The fan-out area has interconnects providing electrical accesses to display elements of the display area. The device has a driver chip disposed on the driver area. The driver chip includes a first edge adjacent to the display area and multiple pad groups, each pad group including a respective row of electronic pads that is (i) arranged substantially in parallel with the first edge and (ii) electrically coupled to a respective subset of display elements via respective interconnects routed on a respective region of the fan-out area. The pad groups include a first pad group and a second pad group. The first and second pad groups have two different distances from the first edge and correspond to two different subsets of interconnects routed on two non-overlapping regions of the fan-out area.

公开(公告)号：US20230045931A1

公开(公告)日：2023-02-16

申请号：US17974407

申请日：2022-10-26

Applicant: Parade Technologies, Ltd.

Inventor： You Ben Yin ,  Quan YU

IPC: G02F1/1345 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00

Abstract: An electronic device has a display substrate including a display area, a driver area, and a fan-out area. The fan-out area has interconnects that provide electrical accesses to display elements on the display area. A driver chip is disposed on the driver area and includes a first edge adjacent to the display area, two side edges connected to the first edge, and a plurality of pad groups. Each pad group includes a row of electronic pads that are electrically coupled to a subset of display elements via a subset of interconnects routed on the fan-out area. The pad groups include a first pad group and a second pad group disposed immediately adjacent to the first pad group. A first subset of interconnects cross one of the two side edges, and extend above a gap between rows of the first and second pad groups to reach the first pad group.

公开(公告)号：US10353517B2

公开(公告)日：2019-07-16

申请号：US15071084

申请日：2016-03-15

Applicant: Parade Technologies Ltd.

Inventor： Ross Martin Fosler

IPC: G06F3/044 ,  G06F3/041

Abstract: A method of processing raw response signals for capacitive sense arrays is performed at an electronic device having one or more processors and a capacitive sense array. The process receives a raw response signal from the capacitive sense array. The process computes an offset signal that represents an average baseline value of the raw response signal over a period of time and filters the raw response signal to a limited frequency band, thereby forming a bandwidth limited signal. The process also computes a differential signal as the difference between the offset signal and the bandwidth limited signal and uses the differential signal to detect an object proximate to the capacitive sense array.

公开(公告)号：US10338439B2

公开(公告)日：2019-07-02

申请号：US15466760

申请日：2017-03-22

Applicant: Parade Technologies, Ltd.

Inventor： Denis Ellis ,  Maksym Prybytko ,  Tim McCarthy

IPC: G06F3/041 ,  G02F1/1343 ,  G06F3/044 ,  G02F1/1368 ,  G02F1/1333

Abstract: This application is directed to detecting touch events using a display pixel array. The display pixel array includes display pixels each of which is disposed between a display electrode and a common electrode. For touch sensing, a processing device drives the subset of common electrodes with an integration voltage that varies by a voltage variation at a predetermined slew rate. The processing device also drives a subset of display electrodes corresponding to the subset of common electrodes in a synchronous manner, thereby reducing an impact of parasitic capacitance associated with the subset of common electrodes. Each of the subset of display electrodes is driven with an adjusted display voltage that varies by the voltage variation at the predetermined slew rate. While driving the subsets of common and display electrodes, a capacitive sense signal associated with the subset of common electrodes is measured at an output of a capacitance sense circuit.

公开(公告)号：US10254879B1

公开(公告)日：2019-04-09

申请号：US15069929

申请日：2016-03-14

Applicant: Parade Technologies, Ltd.

Inventor： Yesim Oral ,  Patrick N Prendergast ,  Tayyar Guzel

IPC: G06F3/041 ,  G06F3/044 ,  G06F3/0488

Abstract: The various implementations described herein include systems, methods and/or devices used to enable touch screen proximity sensing with suppression of false ear touches. An example method is performed at a touch sensitive device and includes enabling or disabling grip suppression to prevent false touches from a user's ear during a phone call based on signals from motion sensors, such as gyroscopes and/or accelerometers, that indicate a direction of the touch sensitive device with respect to a user's face. Another method is performed at a touch sensitive device and includes allowing a user to input on the touch screen a predefined gesture to enable normal touch operation of a touch screen of a touch sensitive device when the device is in a proximity sensing mode.

公开(公告)号：US20190064969A1

公开(公告)日：2019-02-28

申请号：US16118294

申请日：2018-08-30

Applicant: PARADE TECHNOLOGIES, LTD.

Inventor： Andrew Kiernan ,  Fred Jaccard ,  Pete Vavaroutsos

IPC: G06F3/044 ,  G06F3/0354 ,  G06F3/041

Abstract: This application is directed to a capacitive sense array including a two-dimensional array of capacitive sense elements. Each capacitive sense element is formed by a respective intersection of (i) a respective row electrode in a first electrode layer and (ii) a respective column electrode in a second electrode layer. Each column of the capacitive sense elements includes two or more interdigitated column electrodes. Each row electrode forms two or more rows of capacitive sense elements at intersections with the column electrodes.