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公开(公告)号：US12292825B2
公开(公告)日：2025-05-06
申请号：US17726474
申请日：2022-04-21
Applicant: PHISON ELECTRONICS CORP.
Inventor： Sheng-Min Huang , Shih-Ying Song
Abstract: A memory control method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: generating a first operation command via one of a plurality of processing circuits, wherein the first operation command instructs to access a first memory group in a plurality of memory groups; and in response to a first state information, sending a first command sequence to the first memory group according to the first operation command to instruct the first memory group to perform an access operation. The first state information reflects a first activation state of the plurality of memory groups, and the first command sequence does not include a control command sequence configured to activate the first memory group.
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2.发明申请公开(公告)号：US20250125808A1
公开(公告)日：2025-04-17
申请号：US18490767
申请日：2023-10-20
Applicant: PHISON ELECTRONICS CORP.
Inventor： Kun-Ruei Li , Jen-Chu Wu
Abstract: A spread spectrum clock generator, a memory storage device, and a spread spectrum clock generation method are provided. The method includes: generating a spread spectrum clock signal according to a reference clock signal and a control signal; and adjusting the control signal to change a frequency of the spread spectrum clock signal based on multiple frequency change rates, wherein an initial frequency change rate of the spread spectrum clock is greater than a frequency change rate of the spread spectrum clock within a target time range.
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公开(公告)号：US12248699B2
公开(公告)日：2025-03-11
申请号：US18332766
申请日：2023-06-12
Applicant: PHISON ELECTRONICS CORP.
Inventor： Cheng-Jui Chou , Kuen-Chih Lin
Abstract: A clock control circuit, a memory storage device, and a clock control method are disclosed. The method includes: tracking a frequency of a first signal from a host system; generating, in a first mode, a clock signal according to the frequency of the first signal; and generating, in a second mode, the clock signal without reference to the frequency of the first signal.
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公开(公告)号：US12236132B2
公开(公告)日：2025-02-25
申请号：US17573567
申请日：2022-01-11
Applicant: PHISON ELECTRONICS CORP.
Inventor： Sebastien Jean , Ming-Jen Liang
IPC: G06F3/06
Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: sending a first operation command sequence to a rewritable non-volatile memory module to instruct a first memory module in the rewritable non-volatile memory module to perform a first operation; obtaining a first time threshold value corresponding to the first operation; updating a first counting value corresponding to the first memory module; and sending a first query command sequence to the rewritable non-volatile memory module to query a status of the first memory module, in response to that the first counting value reaches the first time threshold value.
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公开(公告)号：US20250036308A1
公开(公告)日：2025-01-30
申请号：US18469561
申请日：2023-09-19
Applicant: PHISON ELECTRONICS CORP.
Inventor： Kok-Yong Tan
IPC: G06F3/06
Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes establishing a connection between the memory storage device and a host system; receiving a first request from the host system via the connection; detecting a status of the memory storage device in a time range according to the first request; and determining whether to use a memory in the host system according to the status.
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Patent Agency Ranking
公开(公告)号：US20240402943A1
公开(公告)日：2024-12-05
申请号：US18349962
申请日：2023-07-11
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yen Chen Yeh
IPC: G06F3/06
Abstract: A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The method is for a rewritable non-volatile memory module including first type physical units and second type physical units. The first type physical units adopt a first operation mode. The second type physical units adopt a second operation mode. The method includes: grouping a part of physical units in the second type physical units to a first reserved region and a second reserved region, and the physical units belonging to the first reserved region and the second reserved region are reserved for usage in a data merging operation; and performing a first data merging operation which includes: collecting first data from a source unit; selecting a target unit from the first reserved region or the second reserved region according to attribute of the source unit; and storing the first data to the target unit.
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7.发明公开公开(公告)号：US20240312949A1
公开(公告)日：2024-09-19
申请号：US18306971
申请日：2023-04-25
Applicant: PHISON ELECTRONICS CORP.
Inventor： Kang-Yun Yang , Yang-Tse Hung , Chao-Cheng Ku , Li-Yuan Lee
CPC classification number: H01L24/49 , G11C5/06 , G11C16/14 , H01L2224/4912
Abstract: A layout structure of differential lines, a memory storage device and a memory control circuit unit are provided. The layout structure of the differential lines includes a wiring layer, a first wire and a second wire. The first wire is arranged on the wiring layer and configured to transmit a first differential signal. The second wire is arranged on the wiring layer and configured to transmit a second differential signal. A first end of the first wire and a first end of the second wire are coupled to a first electrical component. A second end of the first wire and a second end of the second wire are coupled to a second electrical component. The first end of the first wire has a first bending structure. One of the second end of the first wire and the second end of the second wire has a second bending structure.
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公开(公告)号：US20240304259A1
公开(公告)日：2024-09-12
申请号：US18298335
申请日：2023-04-10
Applicant: PHISON ELECTRONICS CORP.
Inventor： Po-Cheng Su , Po-Hao Chen , Yu-Cheng Hsu , Wei Lin
CPC classification number: G11C16/26 , G11C16/08 , G11C16/3404
Abstract: A voltage prediction method, a memory storage device and a memory control circuit unit are disclosed. The method includes: reading a plurality of memory cells in a rewritable non-volatile memory module by using a first read voltage level to obtain count information, and the first read voltage level is configured to distinguish a first state and a second state adjacent to each other in a threshold voltage distribution of the memory cells, and the count information reflects a total number of first memory cells meeting a target condition among the memory cells; and predicting a second read voltage level according to the count information, and the second read voltage level is configured to distinguish a third state and a fourth state adjacent to each other in the threshold voltage distribution.
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9.发明授权公开(公告)号：US12086419B2
公开(公告)日：2024-09-10
申请号：US17866569
申请日：2022-07-18
Applicant: PHISON ELECTRONICS CORP.
Inventor： Chih-Kang Yeh
IPC: G06F3/06
CPC classification number: G06F3/0616 , G06F3/0652 , G06F3/0679
Abstract: A partial erasing management method, a memory storage device, and a memory control circuit unit are provided. The method includes: performing a first partial erasing operation on a first physical region among multiple physical regions in a first physical erasing unit to erase first data in the first physical region; after performing the first partial erasing operation on the first physical region, performing a first programming operation on the first physical region to store second data into the first physical region; and in response to at least one of the first partial erasing operation and the first programming operation, updating first status information related to the first physical region.
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公开(公告)号：US12008242B2
公开(公告)日：2024-06-11
申请号：US17983407
申请日：2022-11-09
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yi-Chung Chen , Ming-Chien Huang
IPC: G06F3/06 , G11C11/4076
CPC classification number: G06F3/0614 , G06F3/0629 , G06F3/0673 , G11C11/4076
Abstract: A signal calibration method, a memory storage device, and a memory control circuit unit are provided. The signal calibration method includes: generating a clock signal and a data strobe signal according to an internal clock signal; respectively transmitting the clock signal and the data strobe signal to a target volatile memory module among multiple volatile memory modules through a first signal path and a second signal path; obtaining a shift value between the data strobe signal and the clock signal at the target volatile memory module; and storing an initial delay setting of the data strobe signal according to delay information of the data strobe signal in response to the shift value being greater than a threshold value.
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