公开(公告)号：US08476773B2

公开(公告)日：2013-07-02

申请号：US12787485

申请日：2010-05-26

Applicant: Stephen Leslie Buchwalter ,  Bruce K. Furman ,  Peter A. Gruber ,  Jae-Woong Nah ,  Da-Yuan Shih

Inventor： Stephen Leslie Buchwalter ,  Bruce K. Furman ,  Peter A. Gruber ,  Jae-Woong Nah ,  Da-Yuan Shih

IPC: H01L23/52

CPC classification number: H01L24/16 ,  H01L21/563 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/12 ,  H01L24/27 ,  H01L24/28 ,  H01L24/31 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L2221/68377 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/1131 ,  H01L2224/11334 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/11822 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/17051 ,  H01L2224/274 ,  H01L2224/29111 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/094 ,  H05K2201/10234 ,  H05K2201/10242 ,  H05K2201/10977 ,  Y02P70/613 ,  Y10T29/49165 ,  H01L2224/45111 ,  H01L2924/01047 ,  H01L2224/13099 ,  H01L2924/01083 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An electrical structure including a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and an interconnect structure electrically and mechanically connecting the first electrically conductive pad to the second electrically conductive pad. The interconnect structure comprises a non-solder metallic core structure, a first solder structure, and a second solder structure. The first solder structure electrically and mechanically connects a first portion of the non-solder metallic core structure to the first electrically conductive pad. The second solder structure electrically and mechanically connects a second portion of the non-solder metallic core structure to the second electrically conductive pad.

Abstract translation: 一种电结构，包括包括第一导电焊盘的第一基板，包括第二导电焊盘的第二基板和将第一导电焊盘电连接和机械连接到第二导电焊盘的互连结构。 互连结构包括非焊料金属芯结构，第一焊料结构和第二焊料结构。 第一焊料结构将非焊料金属芯结构的第一部分电连接并机械地连接到第一导电焊盘。 第二焊料结构将非焊料金属芯结构的第二部分电连接并机械连接到第二导电焊盘。

公开(公告)号：US08342387B2

公开(公告)日：2013-01-01

申请号：US13438505

申请日：2012-04-03

Applicant: Peter A. Gruber ,  Jae-Woong Nah

Inventor： Peter A. Gruber ,  Jae-Woong Nah

IPC: B23K31/02

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L2224/11003 ,  H01L2224/1111 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/3841 ,  H05K3/3478 ,  H05K2203/041 ,  H01L2924/01082 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/0105 ,  H01L2924/00

Abstract: The present disclosure relates to methods of making solder balls having a uniform size. More particularly, the disclosure relates to improved solder ball formation processes that prevent or reduce bridging/merging of two or more solder balls during reflow. The processes of the instant disclosure are desirable because they do not require a sifting step to obtain uniformly-sized solder balls.

Abstract translation: 本公开涉及制造具有均匀尺寸的焊球的方法。 更具体地说，本公开涉及改进的焊球形成过程，其防止或减少回流期间两个或更多个焊球的桥接/合并。 本公开的方法是期望的，因为它们不需要筛选步骤来获得均匀尺寸的焊球。

公开(公告)号：US08328156B2

公开(公告)日：2012-12-11

申请号：US13371840

申请日：2012-02-13

Applicant: Bing Dang ,  Peter A. Gruber ,  Luc Guerin ,  Chirag S. Patel

Inventor： Bing Dang ,  Peter A. Gruber ,  Luc Guerin ,  Chirag S. Patel

IPC: B28B7/22 ,  E04G11/50

CPC classification number: B23K1/0016 ,  B23K3/0623 ,  B23K2101/40 ,  H01L24/11 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/16225 ,  H01L2924/00013 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/29099 ,  H01L2924/00

Abstract: Interconnects are formed on attachment points of a wafer by performing several steps. A plurality of cavities having a predetermined shape is formed in a semiconductor substrate. These cavities are then filled with an interconnect material to form the interconnects. The interconnects are subsequently attached to the attachment points of the wafer.

Abstract translation: 通过执行几个步骤在晶片的附接点上形成互连。 在半导体衬底中形成具有预定形状的多个空腔。 然后用互连材料填充这些空腔以形成互连。 互连随后连接到晶片的附接点。

公开(公告)号：US08242010B2

公开(公告)日：2012-08-14

申请号：US12787503

申请日：2010-05-26

Applicant: Stephen Leslie Buchwalter ,  Bruce K. Furman ,  Peter A. Gruber ,  Jae-Woong Nah ,  Da-Yuan Shih

Inventor： Stephen Leslie Buchwalter ,  Bruce K. Furman ,  Peter A. Gruber ,  Jae-Woong Nah ,  Da-Yuan Shih

IPC: H01L21/44

CPC classification number: H01L24/16 ,  H01L21/563 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/12 ,  H01L24/27 ,  H01L24/28 ,  H01L24/31 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L2221/68377 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/1131 ,  H01L2224/11334 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/11822 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/17051 ,  H01L2224/274 ,  H01L2224/29111 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/094 ,  H05K2201/10234 ,  H05K2201/10242 ,  H05K2201/10977 ,  Y02P70/613 ,  Y10T29/49165 ,  H01L2224/45111 ,  H01L2924/01047 ,  H01L2224/13099 ,  H01L2924/01083 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An electrical interconnect forming method. The electrical interconnect includes a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and an interconnect structure electrically and mechanically connecting the first electrically conductive pad to the second electrically conductive pad. The interconnect structure comprises a non-solder metallic core structure, a first solder structure, and a second solder structure. The first solder structure electrically and mechanically connects a first portion of the non-solder metallic core structure to the first electrically conductive pad. The second solder structure electrically and mechanically connects a second portion of the non-solder metallic core structure to the second electrically conductive pad.

Abstract translation: 电互连形成方法。 电互连包括包括第一导电焊盘的第一衬底，包括第二导电焊盘的第二衬底以及将第一导电焊盘电连接和机械地连接到第二导电焊盘的互连结构。 互连结构包括非焊料金属芯结构，第一焊料结构和第二焊料结构。 第一焊料结构将非焊料金属芯结构的第一部分电连接并机械地连接到第一导电焊盘。 第二焊料结构将非焊料金属芯结构的第二部分电连接并机械连接到第二导电焊盘。

公开(公告)号：US08162203B1

公开(公告)日：2012-04-24

申请号：US13030594

申请日：2011-02-18

Applicant: Peter A. Gruber ,  Jae-Woong Nah

Inventor： Peter A. Gruber ,  Jae-Woong Nah

IPC: B23K31/02

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L2224/11003 ,  H01L2224/1111 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/3841 ,  H05K3/3478 ,  H05K2203/041 ,  H01L2924/01082 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/0105 ,  H01L2924/00

Abstract: The present disclosure relates to methods of making solder balls having a uniform size. More particularly, the disclosure relates to improved solder ball formation processes that prevent or reduce bridging/merging of two or more solder balls during reflow. The processes of the instant disclosure are desirable because they do not require a sifting step to obtain uniformly-sized solder balls.

Abstract translation: 本公开涉及制造具有均匀尺寸的焊球的方法。 更具体地说，本公开涉及改进的焊球形成过程，其防止或减少回流期间两个或更多个焊球的桥接/合并。 本公开的方法是期望的，因为它们不需要筛选步骤来获得均匀尺寸的焊球。

公开(公告)号：US08162199B2

公开(公告)日：2012-04-24

申请号：US12539893

申请日：2009-08-12

Applicant: Eric E. Bourchard ,  Guy Brouillette ,  David H. Danovitch ,  Peter A. Gruber ,  Jean-Luc Landreville

Inventor： Eric E. Bourchard ,  Guy Brouillette ,  David H. Danovitch ,  Peter A. Gruber ,  Jean-Luc Landreville

IPC: B23K3/00 ,  B41F15/44

CPC classification number: B23K3/08 ,  B23K2101/42

Abstract: An apparatus for the removal of excess solder or contaminant, which are encountered on the surfaces of injection mold prior to the transfer of a solder on a silicon wafer. More particularly, there is provided an apparatus for the removal of excess solder, which may be present on a mold surface, without removing any solder, which is located in cavities formed in the mold, and wherein the solder is applied through an injection molded soldering process.

Abstract translation: 一种用于去除在硅晶片上将焊料转移之前在注射模具的表面上遇到的多余焊料或污染物的装置。 更具体地，提供了一种用于去除可能存在于模具表面上的多余焊料的装置，而不去除位于模具中形成的空腔中的任何焊料，并且其中焊料通过注射成型焊接 处理。

公开(公告)号：US08148255B2

公开(公告)日：2012-04-03

申请号：US11856831

申请日：2007-09-18

Applicant: Bing Dang ,  Peter A. Gruber ,  Luc Guerin ,  Chirag S. Patel

Inventor： Bing Dang ,  Peter A. Gruber ,  Luc Guerin ,  Chirag S. Patel

IPC: H01L21/44

CPC classification number: B23K1/0016 ,  B23K3/0623 ,  B23K2101/40 ,  H01L24/11 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/16225 ,  H01L2924/00013 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/29099 ,  H01L2924/00

Abstract: Interconnects are formed on attachment points of a wafer by performing several steps. A plurality of cavities having a predetermined shape is formed in a semiconductor substrate. These cavities are then filled with an interconnect material to form the interconnects. The interconnects are subsequently attached to the attachment points of the wafer.

公开(公告)号：US20110272450A1

公开(公告)日：2011-11-10

申请号：US13186815

申请日：2011-07-20

Applicant: Peter A. Gruber ,  Jae-woong Nah

Inventor： Peter A. Gruber ,  Jae-woong Nah

IPC: B23K3/08 ,  B23K3/06

CPC classification number: H01L24/29 ,  H01L21/486 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/743 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05557 ,  H01L2224/05599 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/27003 ,  H01L2224/271 ,  H01L2224/2732 ,  H01L2224/29006 ,  H01L2224/29015 ,  H01L2224/29076 ,  H01L2224/29083 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32013 ,  H01L2224/32059 ,  H01L2224/3207 ,  H01L2224/73204 ,  H01L2224/743 ,  H01L2224/83101 ,  H01L2224/83203 ,  H01L2224/83345 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  Y10T29/41 ,  Y10T29/5313 ,  Y10T29/53178 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199

Abstract: A die level integrated interconnect decal manufacturing method and apparatus for implementing the method. In accordance with the technology concerning the soldering of integrated circuits and substrates, and particularly providing for solder decal methods forming and utilization, in the present instance there are employed underfills which consist of a solid film material and which are applied between a semiconductor chip and the substrate in order to enhance the reliability of a flip chip package. In particular, the underfill material increases the resistance to fatigue of controlled collapse chip connect (C4) bumps.

公开(公告)号：US20110237030A1

公开(公告)日：2011-09-29

申请号：US12731802

申请日：2010-03-25

Applicant: Peter A. Gruber ,  Jae-Woong Nah

Inventor： Peter A. Gruber ,  Jae-Woong Nah

IPC: H01L21/60

CPC classification number: H01L24/29 ,  H01L21/486 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/743 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05557 ,  H01L2224/05599 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/27003 ,  H01L2224/271 ,  H01L2224/2732 ,  H01L2224/29006 ,  H01L2224/29015 ,  H01L2224/29076 ,  H01L2224/29083 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32013 ,  H01L2224/32059 ,  H01L2224/3207 ,  H01L2224/73204 ,  H01L2224/743 ,  H01L2224/83101 ,  H01L2224/83203 ,  H01L2224/83345 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  Y10T29/41 ,  Y10T29/5313 ,  Y10T29/53178 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199

Abstract: A die level integrated interconnect decal manufacturing method and apparatus for implementing the method. In accordance with the technology concerning the soldering of integrated circuits and substrates, and particularly providing for solder decal methods forming and utilization, in the present instance there are employed underfills which consist of a solid film material and which are applied between a semiconductor chip and the substrate in order to enhance the reliability of a flip chip package. In particular, the underfill material increases the resistance to fatigue of controlled collapse chip connect (C4) bumps.

Abstract translation: 一种用于实现该方法的芯片级集成互连贴花制造方法和装置。 根据关于集成电路和基板的焊接的技术，特别是提供焊接贴花方法的形成和利用，在本实例中，使用由固体膜材料构成的底部填充材料，其被施加在半导体芯片和 衬底，以提高倒装芯片封装的可靠性。 特别地，底部填充材料增加了受控的崩溃芯片连接（C4）凸点的耐疲劳性。

公开(公告)号：US20110233762A1

公开(公告)日：2011-09-29

申请号：US12731793

申请日：2010-03-25

Applicant: Peter A. Gruber ,  Jae-woong Nah

Inventor： Peter A. Gruber ,  Jae-woong Nah

IPC: H01L23/498 ,  H01L21/50

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/563 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/743 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05557 ,  H01L2224/05599 ,  H01L2224/11003 ,  H01L2224/1111 ,  H01L2224/1132 ,  H01L2224/13017 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/27003 ,  H01L2224/271 ,  H01L2224/2732 ,  H01L2224/29006 ,  H01L2224/29015 ,  H01L2224/29076 ,  H01L2224/29083 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/32013 ,  H01L2224/32059 ,  H01L2224/3207 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/743 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83345 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

Abstract: A wafer level integrated interconnect decal manufacturing method and wafer level integrated interconnect decal arrangement. In accordance with the technology concerning the soldering of integrated circuits and substrates, and particularly providing for solder decal methods forming and utilization, in the present instance there are employed underfills which consist of a solid film material and which are applied between a semiconductor chip and the substrate in order to enhance the reliability of a flip chip package. In particular, the underfill material increases the resistance to fatigue of controlled collapse chip connect (C4) bumps.

Abstract translation: 晶圆级集成互连贴花制造方法和晶圆级集成互连贴片布置。 根据关于集成电路和基板的焊接的技术，特别是提供焊接贴花方法的形成和利用，在本实例中，使用由固体膜材料构成的底部填充材料，其被施加在半导体芯片和 衬底，以提高倒装芯片封装的可靠性。 特别地，底部填充材料增加了受控的崩溃芯片连接（C4）凸点的耐疲劳性。