公开(公告)号：US08482336B2

公开(公告)日：2013-07-09

申请号：US13082434

申请日：2011-04-08

Applicant: Pinping Sun ,  Kai D. Feng ,  Essam Mina

Inventor： Pinping Sun ,  Kai D. Feng ,  Essam Mina

IPC: H03K17/687

CPC classification number: H03K17/693 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0928 ,  H01L29/78 ,  H03K17/6221 ,  H03K2017/066 ,  H03K2217/0018

Abstract: A single pole double throw (SPDT) semiconductor switch includes a series connection of a first transmitter-side transistor and a first reception-side transistor between a transmitter node and a reception node. Each of the two first transistors is provided with a gate-side variable impedance circuit, which provides a variable impedance connection between a complementary pair of gate control signals. Further, the body of each first transistor can be connected to a body bias control signal through a body-side variable impedance circuit. In addition, the transmitter node is connected to electrical ground through a second transmitter-side transistor, and the reception node is connected to electrical ground through a second reception-side transistor. Each of the second transistors can have a body bias that is tied to the body bias control signals for the first transistors so that switched-off transistors provide enhanced electrical isolation.

Abstract translation: 单极双掷（SPDT）半导体开关包括在发送器节点和接收节点之间的第一发送器侧晶体管和第一接收侧晶体管的串联连接。 两个第一晶体管中的每一个设置有栅极侧可变阻抗电路，其在互补的一对栅极控制信号之间提供可变阻抗连接。 此外，每个第一晶体管的主体可以通过体侧可变阻抗电路连接到体偏置控制信号。 此外，发射机节点通过第二发射机侧晶体管连接到电接地，并且接收节点通过第二接收侧晶体管连接到电接地。 每个第二晶体管可以具有连接到第一晶体管的体偏置控制信号的体偏置，使得关断晶体管提供增强的电隔离。

公开(公告)号：US20130044838A1

公开(公告)日：2013-02-21

申请号：US13211697

申请日：2011-08-17

Applicant: Hanyi Ding ,  Pinping Sun ,  Hailing Wang

Inventor： Hanyi Ding ,  Pinping Sun ,  Hailing Wang

IPC: H04L27/06 ,  H03B5/08 ,  H03B5/12

CPC classification number: H03B5/1228 ,  H03B5/04 ,  H03B5/1212 ,  H03B5/1243 ,  H03B2200/0034 ,  H04L25/0264

Abstract: A voltage controlled oscillator (VCO), IC and CMOS IC including the VCO. The VCO includes an LC tank circuit, a pair of cross-coupled devices connected to the tank circuit and driving a pair of buffers. Each of the pair of cross-coupled devices includes a field effect transistor (FET) with an independently controllable body, e.g., the surface layer of a Silicon on Insulator (SOI) chip or the surface well of a multi-well chip. Diodes in the multi-well structure are biased off in each device. The tank circuit is coupled to the buffers solely through the FET drain to body capacitance

Abstract translation: 压控振荡器（VCO），IC和CMOS IC包括VCO。 VCO包括LC槽电路，连接到储能电路的一对交叉耦合器件，并驱动一对缓冲器。 这对交叉耦合器件中的每一个包括具有可独立控制的体的场效应晶体管（FET），例如绝缘体上硅（SOI）芯片的表面层或多阱芯片的表面阱。 多孔结构中的二极管在每个器件中偏置。 储能电路仅通过FET漏极耦合到缓冲器到体电容

公开(公告)号：US20120256678A1

公开(公告)日：2012-10-11

申请号：US13082434

申请日：2011-04-08

Applicant: Pinping Sun ,  Kai D. Feng ,  Essam Mina

Inventor： Pinping Sun ,  Kai D. Feng ,  Essam Mina

IPC: H03K17/687

CPC classification number: H03K17/693 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0928 ,  H01L29/78 ,  H03K17/6221 ,  H03K2017/066 ,  H03K2217/0018

Abstract: A single pole double throw (SPDT) semiconductor switch includes a series connection of a first transmitter-side transistor and a first reception-side transistor between a transmitter node and a reception node. Each of the two first transistors is provided with a gate-side variable impedance circuit, which provides a variable impedance connection between a complementary pair of gate control signals. Further, the body of each first transistor can be connected to a body bias control signal through a body-side variable impedance circuit. In addition, the transmitter node is connected to electrical ground through a second transmitter-side transistor, and the reception node is connected to electrical ground through a second reception-side transistor. Each of the second transistors can have a body bias that is tied to the body bias control signals for the first transistors so that switched-off transistors provide enhanced electrical isolation.

Abstract translation: 单极双掷（SPDT）半导体开关包括在发送器节点和接收节点之间的第一发送器侧晶体管和第一接收侧晶体管的串联连接。 两个第一晶体管中的每一个设置有栅极侧可变阻抗电路，其在互补的一对栅极控制信号之间提供可变阻抗连接。 此外，每个第一晶体管的主体可以通过体侧可变阻抗电路连接到体偏置控制信号。 此外，发射机节点通过第二发射机侧晶体管连接到电接地，并且接收节点通过第二接收侧晶体管连接到电接地。 每个第二晶体管可以具有连接到第一晶体管的体偏置控制信号的体偏置，使得关断晶体管提供增强的电隔离。

公开(公告)号：US08779870B2

公开(公告)日：2014-07-15

申请号：US13253260

申请日：2011-10-05

Applicant: Pinping Sun ,  Hanyi Ding ,  Wayne H. Woods, Jr.

Inventor： Pinping Sun ,  Hanyi Ding ,  Wayne H. Woods, Jr.

IPC: H03L5/00 ,  H03H7/24 ,  H01P1/22

CPC classification number: H01P1/22 ,  H03H7/07 ,  H03H7/24 ,  H03H11/245 ,  H03L5/00

Abstract: A low phase variation attenuator uses a combined attenuation path and a phase network to significantly reduce a phase error between a reference signal and an attenuated signal without degrading the insertion loss. A grounded parallel connection of a resistor and a capacitor is employed in series with an attenuation transistor, which is connected to a middle of a two resistor voltage divider. The two resistor voltage divider includes two resistors of equal resistance that are connected in a series connection. The two resistor voltage divider is connected in a parallel connection with a reference transistor, which functions as a main switch for the transmission or attenuation of a radio frequency (RF) signal.

Abstract translation: 低相位变化衰减器使用组合的衰减路径和相位网络来显着地减小参考信号和衰减信号之间的相位误差而不降低插入损耗。 电阻和电容器的并联接地与衰减晶体管串联使用，该衰减晶体管连接到两个电阻分压器的中间。 两个电阻分压器包括两个串联连接的等电阻电阻。 两个电阻分压器与参考晶体管并联连接，参考晶体管用作发射或衰减射频（RF）信号的主开关。

公开(公告)号：US08643191B2

公开(公告)日：2014-02-04

申请号：US13358792

申请日：2012-01-26

Applicant: Hanyi Ding ,  Pinping Sun ,  Guoan Wang ,  Wayne H. Woods, Jr.

Inventor： Hanyi Ding ,  Pinping Sun ,  Guoan Wang ,  Wayne H. Woods, Jr.

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/481 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/1305 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Disclosed is a chip with a power divider/combiner, a module incorporating the chip and associated methods. The divider/combiner comprises first and second metal layers on opposite sides of a substrate. Interconnects extend through the substrate and comprise: a first interconnect, second interconnects annularly arranged about the first interconnect and third interconnects annularly arranged about the second interconnects. Each interconnect comprises one or more through silicon vias lined/filled with a conductor. For a power divider, an opening in the first metal layer at the first interconnect comprises an input port for receiving power and openings in the first or second metal layer at the second interconnects comprise output ports for applying power to other devices. For a power combiner, openings in the first or second metal layer at the second interconnects comprise the input ports and an opening in the first metal layer at the first interconnect comprises an output port.

Abstract translation: 公开了具有功率分配器/组合器的芯片，包括芯片的模块和相关联的方法。 分隔器/组合器包括在衬底的相对侧上的第一和第二金属层。 互连件延伸穿过衬底并且包括：第一互连，围绕第一互连环形布置的第二互连和围绕第二互连环形布置的第三互连。 每个互连包括一个或多个内衬/填充有导体的通孔硅通孔。 对于功率分配器，第一互连处的第一金属层中的开口包括用于接收功率的输入端口，并且在第二互连处的第一或第二金属层中的开口包括用于向其它器件施加电力的输出端口。 对于功率组合器，在第二互连处的第一或第二金属层中的开口包括输入端口，并且在第一互连处的第一金属层中的开口包括输出端口。

公开(公告)号：US08514028B2

公开(公告)日：2013-08-20

申请号：US13211697

申请日：2011-08-17

Applicant: Hanyi Ding ,  Pinping Sun ,  Hailing Wang

Inventor： Hanyi Ding ,  Pinping Sun ,  Hailing Wang

IPC: H03B5/12

CPC classification number: H03B5/1228 ,  H03B5/04 ,  H03B5/1212 ,  H03B5/1243 ,  H03B2200/0034 ,  H04L25/0264

Abstract: A voltage controlled oscillator (VCO), IC and CMOS IC including the VCO. The VCO includes an LC tank circuit, a pair of cross-coupled devices connected to the tank circuit and driving a pair of buffers. Each of the pair of cross-coupled devices includes a field effect transistor (FET) with an independently controllable body, e.g., the surface layer of a Silicon on Insulator (SOI) chip or the surface well of a multi-well chip. Diodes in the multi-well structure are biased off in each device. The tank circuit is coupled to the buffers solely through the FET drain to body capacitance.

Abstract translation: 压控振荡器（VCO），IC和CMOS IC包括VCO。 VCO包括LC槽电路，连接到储能电路的一对交叉耦合器件，并驱动一对缓冲器。 这对交叉耦合器件中的每一个包括具有可独立控制的体的场效应晶体管（FET），例如绝缘体上硅（SOI）芯片的表面层或多阱芯片的表面阱。 多孔结构中的二极管在每个器件中偏置。 储能电路仅通过FET漏极耦合到缓冲器到体电容。

公开(公告)号：US20130193584A1

公开(公告)日：2013-08-01

申请号：US13358792

申请日：2012-01-26

Applicant: Hanyi Ding ,  Pinping Sun ,  Guoan Wang ,  Wayne H. Woods, JR.

Inventor： Hanyi Ding ,  Pinping Sun ,  Guoan Wang ,  Wayne H. Woods, JR.

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/1305 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Disclosed is a chip with a power divider/combiner, a module incorporating the chip and associated methods. The divider/combiner comprises first and second metal layers on opposite sides of a substrate. Interconnects extend through the substrate and comprise: a first interconnect, second interconnects annularly arranged about the first interconnect and third interconnects annularly arranged about the second interconnects. Each interconnect comprises one or more through silicon vias lined/filled with a conductor. For a power divider, an opening in the first metal layer at the first interconnect comprises an input port for receiving power and openings in the first or second metal layer at the second interconnects comprise output ports for applying power to other devices. For a power combiner, openings in the first or second metal layer at the second interconnects comprise the input ports and an opening in the first metal layer at the first interconnect comprises an output port.

Abstract translation: 公开了具有功率分配器/组合器的芯片，包括芯片的模块和相关联的方法。 分隔器/组合器包括在衬底的相对侧上的第一和第二金属层。 互连件延伸穿过衬底并且包括：第一互连，围绕第一互连环形布置的第二互连和围绕第二互连环形布置的第三互连。 每个互连包括一个或多个内衬/填充有导体的通孔硅通孔。 对于功率分配器，第一互连处的第一金属层中的开口包括用于接收功率的输入端口，并且在第二互连处的第一或第二金属层中的开口包括用于向其它器件施加电力的输出端口。 对于功率组合器，在第二互连处的第一或第二金属层中的开口包括输入端口，并且在第一互连处的第一金属层中的开口包括输出端口。

公开(公告)号：US20130088403A1

公开(公告)日：2013-04-11

申请号：US13253260

申请日：2011-10-05

Applicant: Pinping Sun ,  Hanyi Ding ,  Wayne H. Woods, JR.

Inventor： Pinping Sun ,  Hanyi Ding ,  Wayne H. Woods, JR.

IPC: H01Q1/50 ,  G06F17/50 ,  H01P1/22

CPC classification number: H01P1/22 ,  H03H7/07 ,  H03H7/24 ,  H03H11/245 ,  H03L5/00

Abstract: A low phase variation attenuator uses a combined attenuation path and a phase network to significantly reduce a phase error between a reference signal and an attenuated signal without degrading the insertion loss. A grounded parallel connection of a resistor and a capacitor is employed in series with an attenuation transistor, which is connected to a middle of a two resistor voltage divider. The two resistor voltage divider includes two resistors of equal resistance that are connected in a series connection. The two resistor voltage divider is connected in a parallel connection with a reference transistor, which functions as a main switch for the transmission or attenuation of a radio frequency (RF) signal.

Abstract translation: 低相位变化衰减器使用组合的衰减路径和相位网络来显着地减小参考信号和衰减信号之间的相位误差而不降低插入损耗。 电阻和电容器的并联接地与衰减晶体管串联使用，该衰减晶体管连接到两个电阻分压器的中间。 两个电阻分压器包括两个串联连接的等电阻电阻。 两个电阻分压器与参考晶体管并联连接，参考晶体管用作发射或衰减射频（RF）信号的主开关。