公开(公告)号：US20190165375A1

公开(公告)日：2019-05-30

申请号：US16263711

申请日：2019-01-31

Applicant: John Devin MacKenzie ,  Christine Chihfan Ho ,  Karthik Yogeeswaran ,  Po-Jen Cheng

Inventor： John Devin MacKenzie ,  Christine Chihfan Ho ,  Karthik Yogeeswaran ,  Po-Jen Cheng

IPC: H01M4/62 ,  H01M4/42 ,  H01M10/0585 ,  H01M4/04 ,  H01M4/1395 ,  H01M4/1391 ,  H01M10/0565 ,  H01M4/50 ,  H01M4/134 ,  H01M4/131 ,  H01M10/054

CPC classification number: H01M4/62 ,  H01M4/0402 ,  H01M4/06 ,  H01M4/13 ,  H01M4/131 ,  H01M4/134 ,  H01M4/1391 ,  H01M4/1395 ,  H01M4/42 ,  H01M4/502 ,  H01M6/40 ,  H01M10/052 ,  H01M10/054 ,  H01M10/0565 ,  H01M10/0567 ,  H01M10/0568 ,  H01M10/0585 ,  H01M12/06 ,  H01M2004/027 ,  H01M2004/028

Abstract: An electrical or electrochemical cell, including a cathode layer, an electrolyte layer, and an anode layer is disclosed. The cathode layer includes a first material providing a cathodic electric transport, charge storage or redox function. The electrolyte layer includes a polymer, a first electrolyte salt, and/or an ionic liquid. The anode layer includes a second material providing an anodic electric transport, charge storage or redox function. At least one of the cathode and anode layers includes the ionic liquid, a second electrolyte salt, and/or a transport-enhancing additive.

公开(公告)号：US09276292B1

公开(公告)日：2016-03-01

申请号：US13844221

申请日：2013-03-15

Applicant: John Devin MacKenzie ,  Christine Chihfan Ho ,  Karthik Yogeeswaran ,  Po-Jen Cheng

Inventor： John Devin MacKenzie ,  Christine Chihfan Ho ,  Karthik Yogeeswaran ,  Po-Jen Cheng

IPC: H01M10/04 ,  H01M10/40 ,  H01M2/14 ,  H01M2/16 ,  H01M10/0567 ,  H01M10/052 ,  H01M10/058

CPC classification number: H01M10/0567 ,  H01M4/06 ,  H01M4/13 ,  H01M4/62 ,  H01M6/40 ,  H01M10/052 ,  H01M10/0568 ,  H01M12/06

Abstract: An electrical or electrochemical cell, including a cathode layer, an electrolyte layer, and an anode layer is disclosed. The cathode layer includes a first material providing a cathodic electric transport, charge storage or redox function. The electrolyte layer includes a polymer, a first electrolyte salt, and/or an ionic liquid, The anode layer includes a second material providing an anodic electric transport, charge storage or redox function. At least one of the cathode and anode layers includes the ionic liquid, a second electrolyte salt, and/or a transport-enhancing additive.

Abstract translation: 公开了一种电气或电化学电池，包括阴极层，电解质层和阳极层。 阴极层包括提供阴极电输送，电荷存储或氧化还原功能的第一材料。 电解质层包括聚合物，第一电解质盐和/或离子液体。阳极层包括提供阳极电输送，电荷存储或氧化还原功能的第二材料。 阴极和阳极层中的至少一个包括离子液体，第二电解质盐和/或输送增强添加剂。

公开(公告)号：US08288853B2

公开(公告)日：2012-10-16

申请号：US12615852

申请日：2009-11-10

Applicant: Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

Inventor： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

IPC: H01L23/02

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/05099

Abstract: A package comprises a first unit including a semiconductor body, a hole, an isolation layer, a conductive layer and a solder. The semiconductor body has a first surface having a pad and a protection layer exposing the pad. The hole penetrates the semiconductor body. The isolation layer is disposed on the side wall of the hole. The conductive layer covers the pad, a part of the protection layer, and the isolation layer. The lower end of the conductive layer extends to below a second surface of the semiconductor body. The solder is disposed in the hole, and is electrically connected to the pad via the conductive layer. A second unit similar to the first unit and stacked thereon includes a lower end of a second conductive layer that extends to below a second surface of a second semiconductor body and contacts the upper end of the first solder.

Abstract translation: 封装包括包括半导体本体，孔，隔离层，导电层和焊料的第一单元。 半导体本体具有第一表面，其具有衬垫和暴露衬垫的保护层。 孔穿透半导体本体。 隔离层设置在孔的侧壁上。 导电层覆盖焊盘，保护层的一部分和隔离层。 导电层的下端延伸到半导体本体的第二表面的下方。 焊料设置在孔中，并通过导电层与焊盘电连接。 类似于第一单元并且堆叠在其上的第二单元包括延伸到第二半导体本体的第二表面下方并接触第一焊料的上端的第二导电层的下端。

公开(公告)号：US07863181B2

公开(公告)日：2011-01-04

申请号：US12170138

申请日：2008-07-09

Applicant: Hsueh An Yang ,  Po Jen Cheng

Inventor： Hsueh An Yang ,  Po Jen Cheng

IPC: H01L21/4763

CPC classification number: H01L21/0272 ,  H01L21/31144 ,  H01L21/32115 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/051 ,  H01L2224/056 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00014

Abstract: Method for manufacturing a device having a conductive via includes the following steps. A dielectric material layer including a through hole is formed on a substrate. A seed metallic layer is formed on the dielectric material layer and in the through hole. A metallic layer is formed on the seed metallic layer, and is filled in the through hole. The metallic layer located over the seed metallic layer and outside the through hole is etched by a spin etching process, whereby the metallic layer located in the through hole is formed to a lower portion. An upper portion is formed on the lower portion, and a metallic trace is formed on the seed metallic layer, wherein the upper and lower portions is formed to a conductive via, and the conductive via and the metallic trace expose a part of the seed metallic layer. The exposed seed metallic layer is etched.

Abstract translation: 具有导电通孔的装置的制造方法包括以下步骤。 在基板上形成包括通孔的电介质材料层。 在电介质材料层和通孔中形成种子金属层。 在种子金属层上形成金属层，并填充在通孔中。 通过旋转蚀刻工艺蚀刻位于种子金属层上方的金属层和通孔外部，由此将位于通孔中的金属层形成为下部。 在下部形成上部，在种子金属层上形成金属线，其中上部和下部形成为导电通孔，并且导电通孔和金属迹线暴露出种子金属的一部分 层。 暴露的种子金属层被蚀刻。

公开(公告)号：US07642132B2

公开(公告)日：2010-01-05

申请号：US11584546

申请日：2006-10-23

Applicant: Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

Inventor： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

IPC: H01L21/44

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/05099

Abstract: The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a semiconductor body; (b) forming at least one blind hole in the semiconductor body; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) patterning the conductive layer; (f) removing a part of the lower surface of the semiconductor body and a part of the isolation layer, so as to expose a part of the conductive layer; (g) forming a solder on the lower end of the conductive layer; (h) stacking a plurality of the semiconductor bodies, and performing a reflow process; and (i) cutting the stacked semiconductor bodies, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer and the solder thereon are “inserted” into the space formed by the conductive layer of the lower semiconductor body, so as to enhance the joining between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.

Abstract translation: 本发明涉及三维包装及其制造方法。 该方法包括：（a）提供半导体本体; （b）在半导体本体中形成至少一个盲孔; （c）在盲孔的侧壁上形成隔离层; （d）在隔离层上形成导电层; （e）图案化导电层; （f）去除所述半导体主体的下表面的一部分和所述隔离层的一部分，以暴露所述导电层的一部分; （g）在导电层的下端形成焊料; （h）堆叠多个半导体体，进行回流处理; 和（i）切割堆叠的半导体本体，以便形成多个三维封装。 因此，导电层的下端和其上的焊料被“插入”到由下半导体本体的导电层形成的空间中，以便增强导电层和焊料之间的接合，并且有效地减少 加入后三维包装的整体高度。

公开(公告)号：US20090300849A1

公开(公告)日：2009-12-10

申请号：US12430317

申请日：2009-04-27

Applicant: Po-Jen Cheng ,  Li-Hao Cheng ,  Chih-Huang Cheng

Inventor： Po-Jen Cheng ,  Li-Hao Cheng ,  Chih-Huang Cheng

IPC: B01D11/02 ,  D06L1/02

CPC classification number: D06L1/00 ,  D06L1/02

Abstract: The present invention relates to a method of extracting oil of cloth via supercritical fluid, comprises the steps of: a cloth to be extracted is provided in an extracting tank; a gas is filled into a storing tank; a water-cooling machine is provided and served to cool down the temperature of the gas; a pump is provided and served to compress the gas; a water-heating machine is provided and served to raise the temperature of the gas so the gas becomes a supercritical fluid; and the supercritical fluid is inserted into the extracting tank for extracting the oil. By the above mentioned method, the cleanness of the cleanroom wiping cloth can be immediately sensed and obtained, and the gas can be recycled for achieving energy-saving.

Abstract translation: 本发明涉及一种通过超临界流体提取布料的方法，包括以下步骤：提取罐中提取的布料; 将气体填充到储存罐中; 提供了一台水冷机，用来冷却气体的温度; 提供一个泵并用来压缩气体; 提供了一种水加热机，用于提高气体的温度，使气体成为超临界流体; 并将超临界流体插入提取罐中以提取油。 通过上述方法，可以立即检测和获得洁净室擦拭布的清洁度，并且可以再循环气体以实现节能。

公开(公告)号：US07528053B2

公开(公告)日：2009-05-05

申请号：US11645042

申请日：2006-12-26

Applicant: Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

Inventor： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

IPC: H01L21/46 ,  H01L21/4763

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L25/50 ,  H01L2224/48145 ,  H01L2225/06506 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/00012

Abstract: A three-dimensional package and a method of making the same including providing a wafer; forming at least one blind hole in the wafer; forming an isolation layer on the side wall of the blind hole; forming a conductive layer on the isolation layer; forming a dry film on the conductive layer; filling the blind hole with metal; removing the dry film, and patterning the conductive layer; removing a part of the metal in the blind hole to form a space; removing a part of the second surface of the wafer and a part of the isolation layer, to expose a part of the conductive layer; forming a solder on the lower end of the conductive layer, the melting point of the solder is lower than the metal; stacking a plurality of the wafers, and performing a reflow process; and cutting the stacked wafers, to form three-dimensional packages.

Abstract translation: 三维封装及其制造方法，包括提供晶片; 在晶片中形成至少一个盲孔; 在盲孔的侧壁上形成隔离层; 在隔离层上形成导电层; 在导电层上形成干膜; 用金属填充盲孔; 去除干膜，图案化导电层; 去除盲孔中的金属的一部分以形成空间; 去除所述晶片的所述第二表面的一部分和所述隔离层的一部分，以暴露所述导电层的一部分; 在导电层的下端形成焊料，焊料的熔点低于金属; 堆叠多个晶片，并进行回流处理; 并切割堆叠的晶片，以形成三维封装。

公开(公告)号：US07501342B2

公开(公告)日：2009-03-10

申请号：US12050601

申请日：2008-03-18

Applicant: Wei Chung Wang ,  Po Jen Cheng ,  Hsueh An Yang ,  Pei Chun Chen

Inventor： Wei Chung Wang ,  Po Jen Cheng ,  Hsueh An Yang ,  Pei Chun Chen

IPC: H01L21/44

CPC classification number: H01L23/5226 ,  H01L21/02118 ,  H01L21/312 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L2225/06572 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/19041

Abstract: A method for manufacturing a device having a via structure includes the following steps. A seed metallic layer is formed on a substrate. A patterned metallic-trace layer is formed on the seed metallic layer. A positive-type photoresist layer is formed on the patterned metallic-trace layer and seed metallic layer. The photoresist layer is patterned for defining a through hole which exposes a part of the patterned metallic-trace layer, wherein the through hole has a high aspect ratio. A metallic material is electroplated in the through hole so as to form a metallic pillar. The photoresist layer is removed. A part of the seed metallic layer is etched, whereby traces of the patterned metallic-trace layer are electrically isolated from each other. A dielectric material layer is formed on the substrate for sealing the patterned metallic-trace layer and a part of the metallic pillar and exposing a top surface of the metallic pillar.

Abstract translation: 用于制造具有通孔结构的器件的方法包括以下步骤。 种子金属层形成在基片上。 在种子金属层上形成图案化的金属痕迹层。 在图案化的金属痕迹层和种子金属层上形成正型光致抗蚀剂层。 图案化光致抗蚀剂层以限定暴露图案化的金属 - 迹线层的一部分的通孔，其中通孔具有高纵横比。 在通孔中电镀金属材料，形成金属柱。 去除光致抗蚀剂层。 蚀刻种子金属层的一部分，由此图案化的金属迹线层的迹线彼此电隔离。 在基板上形成电介质材料层，用于密封图案化的金属迹线层和金属柱的一部分并暴露金属柱的顶表面。

公开(公告)号：US07297080B2

公开(公告)日：2007-11-20

申请号：US11030451

申请日：2005-01-06

Applicant: William D. Severa ,  Po-Jen Cheng ,  Gerald J. LeVault ,  Donald G. Loeffler

Inventor： William D. Severa ,  Po-Jen Cheng ,  Gerald J. LeVault ,  Donald G. Loeffler

IPC: A63B49/10

CPC classification number: A63B49/03 ,  A63B60/52 ,  A63B60/54

Abstract: A game racquet includes head portion and a handle portion. The head and handle portions include one or both of a fiber-reinforced thermoset material and a fiber-reinforced thermoplastic material. The handle portion is coupled to the head portion by shock and/or vibration absorbing material.

Abstract translation: 游戏球拍包括头部和手柄部。 头部和手柄部分包括纤维增强热固性材料和纤维增强热塑性材料中的一种或两种。 手柄部分通过冲击和/或振动吸收材料联接到头部。

公开(公告)号：US07125745B2

公开(公告)日：2006-10-24

申请号：US10833087

申请日：2004-04-28

Applicant: Kun-Ching Chen ,  Yi-Chuan Ding ,  Po-Jen Cheng ,  Chih-Ming Chung ,  Yun-Hsiang Tien

Inventor： Kun-Ching Chen ,  Yi-Chuan Ding ,  Po-Jen Cheng ,  Chih-Ming Chung ,  Yun-Hsiang Tien

IPC: H01L21/44

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/11 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A multi-chip package substrate for both flip-chip bumping and wire-bonding applications comprises a substrate body having a top surface and a bottom surface. A plurality of bumping pads and a plurality of wire-bonding pads are formed on the top surface. The bumping pads are disposed on the top surface of the substrate body and a pre-solder material is formed on the bumped pads. The wire-bonding pads are disposed on the top surface of the substrate body and a Ni/Au layer is formed on the wire-bonding pads. In order to avoid the bumping pads and the wire-bonding pads from oxidation during packaging processes. The pre-solder material fully covers the bumping pads to avoid the Au intermetallics generated in a plurality of bumps on a bumped chip during packaging processes. The reliability of the multi-chip stacked package for both flip-chip bumping and wire-bonding applications will be greatly improved.

Abstract translation: 用于倒装芯片凸块和引线接合应用的多芯片封装衬底包括具有顶表面和底表面的衬底本体。 多个凸台和多个引线接合垫形成在顶表面上。 凸起垫设置在基板主体的顶表面上，并且在凸起的焊盘上形成预焊材料。 引线接合焊盘设置在基板主体的顶表面上，并且在引线接合焊盘上形成Ni / Au层。 为了避免在包装过程中碰撞垫和引线接合垫发生氧化。 预焊材料完全覆盖凸块，以避免在包装过程中在凸起芯片上的多个凸块中产生的Au金属间化合物。 用于倒装芯片凸块和引线接合应用的多芯片堆叠封装的可靠性将大大提高。