公开(公告)号：US20250165420A1

公开(公告)日：2025-05-22

申请号：US19028524

申请日：2025-01-17

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G06F13/362 ,  G06F13/40 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4096 ,  G11C14/00 ,  G11C16/10 ,  G11C16/26 ,  H01L23/00 ,  H01L23/48 ,  H01L23/50 ,  H01L23/60 ,  H01L25/065 ,  H10D89/60

Abstract: This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device.

公开(公告)号：US20250156348A1

公开(公告)日：2025-05-15

申请号：US18959973

申请日：2024-11-26

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Arun Vaidyanath ,  Sanku Mukherjee

IPC: G06F13/16 ,  G06F1/3234 ,  G06F12/02 ,  G06F13/40

Abstract: An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

公开(公告)号：US20250141434A1

公开(公告)日：2025-05-01

申请号：US18939768

申请日：2024-11-07

Applicant: Rambus Inc.

Inventor： Cosmin Iorga

IPC: H03K3/0232 ,  G11C7/22 ,  H03K19/17784 ,  H03L7/081 ,  H03L7/099 ,  H03L7/195

Abstract: Described is an integrated circuit with a driving amplifier that transmits a signal over a link (e.g. a wire) by raising and lowering a voltage on the link. A reference oscillator provides an error measure for the rate at which the voltage transitions between voltages, the slew rate. Slew-rate calibration circuitry adjusts the driving amplifier responsive to the error measure.

公开(公告)号：US20250139030A1

公开(公告)日：2025-05-01

申请号：US18944887

申请日：2024-11-12

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness

IPC: G06F13/16

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory controller is disclosed. The memory controller includes write queue logic that has first storage to temporarily store signal components of a write operation. The signal components include an address and write data. A transfer interface issues the signal components of the write operation to a bank of a storage class memory (SCM) device and generates a time value. The time value represents a minimum time interval after which a subsequent write operation can be issued to the bank. The write queue logic includes an issue queue to store the address and the time value for a duration corresponding to the time value.

公开(公告)号：US20250139029A1

公开(公告)日：2025-05-01

申请号：US18941090

申请日：2024-11-08

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Christopher Haywood

IPC: G06F13/16 ,  G06F13/40

Abstract: In a modular memory system, a memory control component, first and second memory sockets and data buffer components are all mounted to the printed circuit board. The first and second memory sockets have electrical contacts to electrically engage counterpart electrical contacts of memory modules to be inserted therein, and each of the data buffer components includes a primary data interface electrically coupled to the memory control component, and first and second secondary data interfaces electrically coupled to subsets of the electrical contacts within the first and second memory sockets, respectively.

公开(公告)号：US20250119148A1

公开(公告)日：2025-04-10

申请号：US18927163

申请日：2024-10-25

Applicant: Rambus Inc.

Inventor： Panduka WIJETUNGA ,  Catherine Chen

IPC: H03L7/081 ,  H03L7/097

Abstract: A phase-locked loop or delay locked loop provides a coarse alignment between an input clock and an output clock. A latch receiver circuit provides an indicator of a delay error between the input clock and the output clock. The delay error is used by a control circuit or state machine to adjust a fine delay that affects the output clock signal timing relative to the input clock signal. The fine delay is adjusted to minimize the timing difference between the output clock signal and the input clock signal.

公开(公告)号：US12267187B1

公开(公告)日：2025-04-01

申请号：US17901780

申请日：2022-09-01

Applicant: Rambus Inc.

Inventor： Masum Hossain ,  Jared L. Zerbe

IPC: H04L25/03 ,  H03L7/00 ,  H03L7/08 ,  H04L7/00 ,  H04L7/033 ,  H04L25/08

Abstract: This disclosure provides a split-path equalizer and a clock recovery circuit. More particularly, clock recovery operation is enhanced, particularly at high-signaling rates, by separately equalizing each of a data path and an edge path. In specific embodiments, the data path is equalized in a manner that maximizes signal-to-noise ratio and the edge path is equalized in a manner that emphasizes symmetric edge response for a single unit interval and zero edge response for other unit intervals (e.g., irrespective of peak voltage margin). Such equalization tightens edge grouping and thus enhances clock recovery, while at the same time optimizing data-path sampling. Techniques are also disclosed for addressing split-path equalization-induced skew.

公开(公告)号：US12253903B2

公开(公告)日：2025-03-18

申请号：US18140133

申请日：2023-04-27

Applicant: Rambus Inc.

Inventor： Yuanlong Wang ,  Frederick A. Ware

IPC: G06F11/07 ,  G06F3/06 ,  G06F11/10 ,  G06F11/14 ,  G06F13/42 ,  H03M13/00 ,  H03M13/09 ,  H03M13/29 ,  H04L1/00 ,  H04L1/08 ,  H04L1/1867

Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

公开(公告)号：US12249399B2

公开(公告)日：2025-03-11

申请号：US18680395

申请日：2024-05-31

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Kyung Suk Oh

IPC: G11C5/06 ,  G11C7/22 ,  G11C11/4063 ,  G11C29/02 ,  G11C5/02 ,  G11C5/04 ,  G11C7/18 ,  G11C11/4097

Abstract: A memory device includes a set of inputs, and a first register that includes a first register field to store a value for enabling application of one of a plurality of command/address (CA) on-die termination (ODT) impedance values to first inputs that receive the CA signals; and a second register field to store a value for enabling application of one of a plurality of chip select (CS) ODT impedance values to a second input that receives the CS signal. A third register field may store a value for enabling application of a clock (CK) ODT impedance value to third inputs that receive the CK signal.

公开(公告)号：US12249392B2

公开(公告)日：2025-03-11

申请号：US18388680

申请日：2023-11-10

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

IPC: G11C16/04 ,  G06F12/00 ,  G06F13/16 ,  G11C7/10

Abstract: A memory controller includes a register to store phase offset value. The phase offset value represents a phase relationship between a memory request signal component and a reference signal. The phase offset value is established through write and read back testing. Transmit circuitry applies the phase offset value in launching the memory request signal component from the IC memory controller to an IC memory device.