公开(公告)号：US07642569B2

公开(公告)日：2010-01-05

申请号：US12366425

申请日：2009-02-05

Applicant: David R. Greenberg ,  Shwu-Jen Jeng

Inventor： David R. Greenberg ,  Shwu-Jen Jeng

IPC: H01L29/737

CPC classification number: H01L29/66287 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/42308 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

Abstract: A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided.

Abstract translation: 提供了具有最小化寄生效应的晶体管，其包括在本征发射极部分顶部具有凹入的非本征发射极部分的发射极; 包括与本征发射极部分电接触的本征基极部分的基极和与本征基极部分电接触并且通过一组发射极/基底间隔物与凹入的非本征发射极部分电隔离的非本征基极部分; 以及与本征基部电接触的集电体。 晶体管可以进一步包括具有完全硅化到发射极/基极间隔物的顶表面的外在基极。 另外，晶体管可以包括在晶体管的有效区域内的基极窗口。 还提供了形成上述晶体管的方法。

公开(公告)号：US07022246B2

公开(公告)日：2006-04-04

申请号：US10336992

申请日：2003-01-06

Applicant: Anil K. Chinthakindi ,  Shwu-Jen Jeng ,  Michael F. Lofaro ,  Christopher M. Schnabel ,  Kenneth J. Stein

Inventor： Anil K. Chinthakindi ,  Shwu-Jen Jeng ,  Michael F. Lofaro ,  Christopher M. Schnabel ,  Kenneth J. Stein

IPC: H01L21/302

CPC classification number: H01L28/20 ,  H01L23/5223 ,  H01L27/0802 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  Y10S438/97 ,  Y10T29/49082 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A method is disclosed of fabricating a MIMCAP (a capacitor (CAP) formed by successive layers of metal, insulator, metal (MIM)) and a thin film resistor at the same level. A method is also disclosed of fabricating a MIMCAP and a thin film resistor at the same level, and a novel integration scheme for BEOL (back-end-of-line processing) thin film resistors which positions them closer to FEOL (front-end-of-line processing) devices.

Abstract translation: 公开了制造MIMCAP（由金属，绝缘体，金属（MIM）的连续层形成的电容器（CAP））和同一水平的薄膜电阻器的方法。 还公开了制造相同水平的MIMCAP和薄膜电阻器的方法，以及用于BEOL（后端处理）薄膜电阻器的新颖的集成方案，使它们更接近FEOL（前端 - 线上处理）设备。

公开(公告)号：US5282925A

公开(公告)日：1994-02-01

申请号：US973380

申请日：1992-11-09

Applicant: Shwu-Jen Jeng ,  Wesley C. Natzle ,  Chienfan Yu

Inventor： Shwu-Jen Jeng ,  Wesley C. Natzle ,  Chienfan Yu

IPC: C23F4/00 ,  H01L21/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06

CPC classification number: H01L21/67069 ,  H01L21/31116

Abstract: New device and method are described for accurate etching and removal of thin layer by controlling the surface residence time, thickness and composition of reactant containing film. Etching of silicon dioxide at low pressure using a quartz crystal microbalance is illustrated. Usefulness of the invention in the manufacture of microelectronic devices is shown.

Abstract translation: 描述了通过控制含反应物膜的表面停留时间，厚度和组成来精确蚀刻和去除薄层的新装置和方法。 示出了使用石英晶体微量天平在低压下的二氧化硅蚀刻。 示出了本发明在制造微电子器件中的用途。

公开(公告)号：US07491617B2

公开(公告)日：2009-02-17

申请号：US11764388

申请日：2007-06-18

Applicant: David R. Greenberg ,  Shwu-Jen Jeng

Inventor： David R. Greenberg ,  Shwu-Jen Jeng

IPC: H01L21/331

CPC classification number: H01L29/66287 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/42308 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

Abstract: A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided.

Abstract translation: 提供了具有最小化寄生效应的晶体管，其包括在本征发射极部分顶部具有凹入的非本征发射极部分的发射极; 包括与本征发射极部分电接触的本征基极部分的基部和与本征基极部分电接触并且通过一组发射极/基底间隔物与凹入的非本征发射极部分电隔离的非本征基极部分; 以及与本征基部电接触的集电体。 晶体管可以进一步包括具有完全硅化到发射极/基极间隔物的顶表面的外在基极。 另外，晶体管可以包括在晶体管的有效区域内的基极窗口。 还提供了形成上述晶体管的方法。

公开(公告)号：US20080057673A1

公开(公告)日：2008-03-06

申请号：US11841018

申请日：2007-08-20

Applicant: Xiaomeng CHEN ,  Shwu-Jen JENG ,  Byeong Y. KIM ,  Hasan M. NAYFEH

Inventor： Xiaomeng CHEN ,  Shwu-Jen JENG ,  Byeong Y. KIM ,  Hasan M. NAYFEH

IPC: H01L21/76

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78

Abstract: The invention is directed to a structure and method of forming a structure having a sealed gate oxide layer. The structure includes a gate oxide layer formed on a substrate and a gate formed on the gate oxide layer. The structure further includes a material abutting walls of the gate and formed within an undercut underneath the gate to protect regions of the gate oxide layer exposed by the undercut. Source and drain regions are isolated from the gate by the material.

公开(公告)号：US07253070B2

公开(公告)日：2007-08-07

申请号：US11481070

申请日：2006-07-05

Applicant: David R. Greenberg ,  Shwu-Jen Jeng

Inventor： David R. Greenberg ,  Shwu-Jen Jeng

IPC: H01L21/8222

CPC classification number: H01L29/66287 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/42308 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

Abstract: A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided.

Abstract translation: 提供了具有最小化寄生效应的晶体管，其包括在本征发射极部分顶部具有凹入的非本征发射极部分的发射极; 包括与本征发射极部分电接触的本征基极部分的基部和与本征基极部分电接触并且通过一组发射极/基底间隔物与凹入的非本征发射极部分电隔离的非本征基极部分; 以及与本征基部电接触的集电体。 晶体管可以进一步包括具有完全硅化到发射极/基极间隔物的顶表面的外在基极。 另外，晶体管可以包括在晶体管的有效区域内的基极窗口。 还提供了形成上述晶体管的方法。

公开(公告)号：US20060249814A1

公开(公告)日：2006-11-09

申请号：US11481070

申请日：2006-07-05

Applicant: David Greenberg ,  Shwu-Jen Jeng

Inventor： David Greenberg ,  Shwu-Jen Jeng

IPC: H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC classification number: H01L29/66287 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/42308 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

Abstract: A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided.

公开(公告)号：US20050191911A1

公开(公告)日：2005-09-01

申请号：US10789282

申请日：2004-02-27

Applicant: David Greenberg ,  Shwu-Jen Jeng

Inventor： David Greenberg ,  Shwu-Jen Jeng

IPC: H01L21/331 ,  H01L29/08 ,  H01L29/423 ,  H01L29/72 ,  H01L29/73 ,  H01L29/732

CPC classification number: H01L29/66287 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/42308 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

Abstract: A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided.

Abstract translation: 提供了具有最小化寄生效应的晶体管，其包括在本征发射极部分顶部具有凹入的非本征发射极部分的发射极; 包括与本征发射极部分电接触的本征基极部分的基极和与本征基极部分电接触并且通过一组发射极/基底间隔物与凹入的非本征发射极部分电隔离的非本征基极部分; 以及与本征基部电接触的集电体。 晶体管可以进一步包括具有完全硅化到发射极/基极间隔物的顶表面的外在基极。 另外，晶体管可以包括在晶体管的有效区域内的基极窗口。 还提供了形成上述晶体管的方法。

公开(公告)号：US5423940A

公开(公告)日：1995-06-13

申请号：US114710

申请日：1993-08-31

Applicant: Lee Chen ,  Shwu-Jen Jeng ,  Wesley C. Natzle ,  Chienfan Yu

Inventor： Lee Chen ,  Shwu-Jen Jeng ,  Wesley C. Natzle ,  Chienfan Yu

IPC: C23F4/02 ,  C23F4/00 ,  H01L21/302 ,  H01L21/311 ,  H01J21/00

CPC classification number: H01L21/31116 ,  C23F4/00

Abstract: In supersonic molecular beam etching, the reactivity of the etchant gas and substrate surface is improved by creating etchant gas molecules with high internal energies through chemical reactions of precursor molecules, forming clusters of etchant gas molecules in a reaction chamber, expanding the etchant gas molecules and clusters of etchant gas molecules through a nozzle into a vacuum, and directing the molecules and clusters of molecules onto a substrate. Translational energy of the molecules and clusters of molecules can be improved by seeding with inert gas molecules. The process provides improved controllability, surface purity, etch selectivity and anisotropy. Etchant molecules may also be expanded directly (without reaction in a chamber) to produce clusters whose translational energy can be increased through expansion with a seeding gas.

Abstract translation: 在超音速分子束蚀刻中，蚀刻剂气体和衬底表面的反应性通过通过前体分子的化学反应产生具有高内能的蚀刻剂气体分子来改善，在反应室中形成蚀刻剂气体分子簇，使蚀刻剂气体分子膨胀， 蚀刻剂气体分子的簇通过喷嘴进入真空，并将分子和分子簇引导到基底上。 可以通过用惰性气体分子进行接种来改善分子和分子团簇的平移能。 该方法提供改进的可控性，表面纯度，蚀刻选择性和各向异性。 蚀刻剂分子也可以直接扩增（在室中没有反应）以产生其平移能量可以通过用接种气体膨胀而增加的簇。

公开(公告)号：US5374481A

公开(公告)日：1994-12-20

申请号：US102399

申请日：1993-08-05

Applicant: Shwu Jen Jeng ,  Jerzy Kanicki ,  David E. Kotecki ,  Christopher C. Parks ,  Zu-Jean Tien

Inventor： Shwu Jen Jeng ,  Jerzy Kanicki ,  David E. Kotecki ,  Christopher C. Parks ,  Zu-Jean Tien

IPC: H01L29/43 ,  H01L21/205 ,  H01L21/225 ,  H01L21/28 ,  H01L21/331 ,  H01L29/45 ,  H01L29/73 ,  H01L29/737 ,  H01L29/72

CPC classification number: H01L29/456 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/2256 ,  H01L29/7375 ,  Y10T428/265

Abstract: A polyemitter structure having a thin interfacial layer deposited between the polysilicon emitter contact and the crystalline silicon emitter, as opposed to a regrown SiO.sub.x layer, has improved reproducibility and performance characteristics. A n-doped hydrogenated microcrystalline silicon film can be used as the deposited interfacial film between a crystalline silicon emitter and a polycrystalline silicon contact.

Abstract translation: 与重新生长的SiO x层相反，具有沉积在多晶硅发射极接触和晶体硅发射极之间的薄界面层的聚合物结构具有改进的再现性和性能特性。 可以使用n掺杂的氢化微晶硅膜作为结晶硅发射极和多晶硅接触之间的沉积界面膜。