公开(公告)号：US12292826B2

公开(公告)日：2025-05-06

申请号：US18663114

申请日：2024-05-14

Applicant: Silicon Motion, Inc.

Inventor： Tsai-Cheng Lin ,  Chun-Kun Lee

IPC: G06F12/02 ,  G06F12/1009

Abstract: A method for managing a memory apparatus including a non-volatile (NV) memory element having a plurality of physical blocks includes: obtaining a first host address and first data from a first access command; obtaining a second host address and second data from a second access command; linking the first host address to a first page of the physical block and the second host address to a second page of the physical block; storing the first data and second data into the physical block; building a valid page position table and storing the valid page position table in the volatile memory; and building a global page address linking table and storing the global page address linking table in the volatile memory. The valid page position table and the global page address linking table are loaded from the volatile memory and stored to the NV memory element at predetermined time periods.

公开(公告)号：US12277330B2

公开(公告)日：2025-04-15

申请号：US18219101

申请日：2023-07-07

Applicant: Silicon Motion, Inc.

Inventor： Po-Lin Wu

IPC: G06F3/06

Abstract: A data storage device includes a memory device and a memory controller. The memory device includes multiple memory blocks which include one or more spare memory blocks not written with data and one or more predetermined memory blocks that are configured as a buffer for receiving data from a host device. The memory controller obtains a total number of remaining erasable count of the memory blocks and determines a setting value of a number of said one or more predetermined memory blocks according to a number of currently remaining spare memory block(s), a number of the predetermined memory block(s) that has/have been written with data among said one or more predetermined memory blocks, a predetermined threshold and the total number of remaining erasable count of the memory blocks, and configures the number of the predetermined memory block(s) as the buffer according to the setting value.

公开(公告)号：US12277326B2

公开(公告)日：2025-04-15

申请号：US18236407

申请日：2023-08-22

Applicant: Silicon Motion, Inc.

Inventor： Jie-Hao Lee ,  Keng-Yuan Hsu ,  Po-Cheng Lai

IPC: G06F3/06

Abstract: A method for performing data access management of a memory device in predetermined communications architecture with aid of unbalanced table update size and associated apparatus are provided. The memory device may be arranged to receive a set of first commands, receive a set of first data with a first active block according to the set of first commands, and update a temporary physical-to-logical (P2L) address mapping table corresponding to the first active block, and determine a selected table update size among multiple predetermined table update sizes such as multiple table entry counts and update at least one logical-to-physical address mapping table according to a set of P2L table entries corresponding to the selected table update size in the temporary P2L address mapping table, where the table update size may be dynamically changed for enhancing overall performance.

公开(公告)号：US12277288B2

公开(公告)日：2025-04-15

申请号：US18213907

申请日：2023-06-26

Applicant: Silicon Motion, Inc.

Inventor： Fu-Jen Shih

IPC: G06F3/041 ,  G06F11/10 ,  G06F11/30 ,  G06F13/16

Abstract: An interface circuit includes multiple signal processing devices and a monitor and calibration module including multiple monitoring circuits, multiple calibration circuits and a compensation control mechanism operation logic. The monitoring circuits monitor a reception signal, a transmission signal, a power supplying voltage and a ground voltage to correspondingly generate monitored results. The calibration circuits perform a calibration operation on at least one signal processing device to adjust a characteristic value of the signal processing device. The compensation control mechanism operation logic generates a calibration control signal to control the calibration operation of the calibration circuits based on the monitored results and includes a compensation control mechanism selection circuit which selects a corresponding compensation control mechanism according to the monitored results and set it as a currently-operating compensation control mechanism to control the hardware circuits to operate in compliance with the currently-operating compensation control mechanism.

公开(公告)号：US12265749B2

公开(公告)日：2025-04-01

申请号：US18487324

申请日：2023-10-16

Applicant: Silicon Motion, Inc.

Inventor： Xiaobing Qian

IPC: G06F3/14 ,  G06F3/147

Abstract: A video wall system with software running on a host computer and a video wall control device is shown. Using the software, the user inputs the size of each screen of a video wall and, accordingly, the delay time for each row of screens of the video wall is calculated. The video wall control device couples the host computer to the screens. The video wall control device outputs a plurality of split videos to the different screens through separated output ports, and drives each row of screens to display according to the delay time calculated for the row of screens.

公开(公告)号：US12265469B2

公开(公告)日：2025-04-01

申请号：US18380568

申请日：2023-10-16

Applicant: SILICON MOTION INC.

Inventor： Chao-Kuei Hsieh

IPC: G06F12/02 ,  G06F3/06 ,  G06F3/08 ,  G11C7/10 ,  G11C7/20 ,  G11C16/16 ,  G11C16/26

Abstract: A flash memory controller includes a processing circuit which is arranged for receiving a first command and a first portion address parameter, receiving a second command and a second portion address parameter, obtaining a complete address parameter by combining the first portion address parameter with the second portion address parameter, and performing a corresponding operation upon a flash memory according to the complete address parameter and a command type of the second command.

公开(公告)号：US20250103211A1

公开(公告)日：2025-03-27

申请号：US18731370

申请日：2024-06-03

Applicant: Silicon Motion, Inc.

Inventor： Wei-Ya Lee

IPC: G06F3/06

Abstract: The present invention provides a host device coupled to a memory device, wherein the host device includes a processor, and the processor is configured to perform the steps of: (a) configuring a plurality of transport request descriptors in a memory; (b) writing a plurality of command descriptors into the memory in sequence, wherein a number of the command descriptors is greater than a number of the transport request descriptors; (c) selecting a transport request descriptor from the transport request descriptors sequentially and repeatedly, and determining a command descriptor sequentially without repetition; (d) modifying the transport request descriptor according to the command descriptor; (e) reading the transport request descriptor to send a command in the command descriptor to the memory device; and (f) determining whether a last command descriptor has been processed, if not, going back to step (c), and executing steps (c)-(f) in sequence.

公开(公告)号：US12260123B1

公开(公告)日：2025-03-25

申请号：US18370379

申请日：2023-09-19

Applicant: Silicon Motion, Inc.

Inventor： Fahao Li

IPC: G06F3/06

Abstract: A method for performing data access control of a memory device and associated apparatus are provided. The method may include: receiving a plurality of host commands from a host device, for performing data access including data reading on the NV memory according to the plurality of host commands; and performing a reading parameter learning procedure to generate predicted data of a predicted reading voltage parameter offset regarding adjustment of a reading voltage parameter, for maintaining correctness of the data reading, for example: scanning for a best value, and adding latest information comprising the best value into a data set among one or more data sets in at least one reading-voltage control database; performing local linear regression according to the data set to update a reading voltage prediction function corresponding to a reading voltage prediction model; and generating or updating the predicted data according to the reading voltage prediction function.

公开(公告)号：US12254219B2

公开(公告)日：2025-03-18

申请号：US18361150

申请日：2023-07-28

Applicant: Silicon Motion, Inc.

Inventor： Hsu-Ping Ou ,  Kuang-Ting Tai

IPC: G06F3/06

Abstract: A technique for signal deskew at the non-volatile memory side. The non-volatile memory includes a plurality of dies and a signal timing adjustment circuit. The dies are grouped into storage zones. A controller is coupled to the non-volatile memory through a plurality of data lines. Through the data lines, the controller issues a plurality of commands to provide zone delay parameters to the non-volatile memory to drive the signal timing adjustment circuit at the non-volatile memory side to separately adjust data-line timing of the different storage zones.

公开(公告)号：US12254202B2

公开(公告)日：2025-03-18

申请号：US18123336

申请日：2023-03-20

Applicant: Silicon Motion, Inc.

Inventor： Kun-Cheng Lai ,  Yen-Yu Jou

IPC: G06F3/06

Abstract: The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, the flash memory module comprises a plurality of blocks, and the control method comprising: receiving a settling command from a host device; in response to the settling command, configuring at least one portion of the flash memory module as a zoned namespace, wherein the zoned namespace logically comprises a plurality of zones; generating parameter information according to a configuration of the zoned namespace; and transmitting the parameter information to the host device, for the host device uses the parameter information to set the zone.