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    Trap filtering within a device management protocol
    1.
    发明授权
    Trap filtering within a device management protocol 有权
    陷阱过滤设备管理协议

    公开(公告)号：US09413615B1

    公开(公告)日：2016-08-09

    申请号：US13411248

    申请日：2012-03-02

    Applicant: Vivek Singh ,  Subodh Kumar

    Inventor： Vivek Singh ,  Subodh Kumar

    IPC: G06F15/177 ,  H04L12/24

    CPC classification number: H04L41/22 ,  H04L41/0213 ,  H04L41/0604 ,  H04L41/0681

    Abstract: An example device includes a processor that provides an execution environment for a management agent, and a data repository configured to store configuration information. The management agent is operable to retrieve configuration information that specifies one or more trap conditions and one or more filter criteria from the data repository, detect that at least one of the one or more trap conditions is met, generate a message that includes a set of variable identifiers and associated variable values based on the one or more met trap conditions, determine whether at least one of the variable identifiers and associated value pairs included in the generated messages meet at least one of the filter criteria by at least comparing a variable value of a respective filter criteria to the variable value of the generated message, and selectively send the generated message to a device management system based on the comparison.

    Abstract translation: 示例设备包括为管理代理提供执行环境的处理器和被配置为存储配置信息的数据存储库。 管理代理可操作地从数据存储库中检索指定一个或多个陷阱条件和一个或多个过滤标准的配置信息，检测到满足一个或多个陷阱条件中的至少一个，生成包括一组 基于所述一个或多个满足陷阱条件的变量标识符和相关联的变量值，通过至少将可生成的消息中的变量值与 针对生成的消息的变量值的相应过滤器标准，并且基于该比较选择性地将生成的消息发送到设备管理系统。

    Error handling for device management configuration and operational data retrieval commands
    2.
    发明授权
    Error handling for device management configuration and operational data retrieval commands 有权
    设备管理配置和操作数据检索命令的错误处理

    公开(公告)号：US08549119B1

    公开(公告)日：2013-10-01

    申请号：US12755269

    申请日：2010-04-06

    Applicant: Vivek Singh ,  Subodh Kumar

    Inventor： Vivek Singh ,  Subodh Kumar

    IPC: G06F15/177 ,  G06F15/173

    CPC classification number: H04L41/0853 ,  H04L41/0213 ,  H04L41/046 ,  H04L41/0695 ,  H04L41/0866

    Abstract: An example network management device includes a network management module, and a reconstruction module. The network management module is configured to generate a data retrieval command to direct a managed device to retrieve a set of management variables stored within a database within the managed network device and send the data retrieval command to the managed device. The reconstruction module is configured to receive a plurality of partial responses generated by a deconstruction module of the managed device in response to receiving the data retrieval command and determining that the set of management variables does not fit in a single response, and combine the received plurality of partial responses into the requested set of management variables, wherein each of the plurality of partial responses is received as a separate message from the managed network device and includes a different portion of the requested set of management variables.

    Abstract translation: 示例性网络管理设备包括网络管理模块和重建模块。 网络管理模块被配置为生成数据检索命令以指导被管理设备检索存储在受管网络设备内的数据库内的一组管理变量，并将数据检索命令发送到被管理设备。 重建模块被配置为响应于接收到数据检索命令并且确定该组管理变量不适合单个响应而接收由被管理设备的解构模块生成的多个部分响应，并且将接收的多个 部分响应到所请求的一组管理变量中，其中多个部分响应中的每一个作为来自被管理网络设备的单独消息被接收，并且包括所请求的一组管理变量的不同部分。

    Determining timing paths within a circuit block of a programmable integrated circuit
    3.
    发明授权
    Determining timing paths within a circuit block of a programmable integrated circuit 有权
    确定可编程集成电路的电路块内的定时路径

    公开(公告)号：US08117577B1

    公开(公告)日：2012-02-14

    申请号：US12361516

    申请日：2009-01-28

    Applicant: Vasisht M. Vadi ,  Alvin Y. Ching ,  Subodh Kumar ,  Richard D. Freeman ,  Ian L. McEwen ,  Philip R. Haratsaris ,  Jaime D. Lujan ,  Eric M. Schwarz

    Inventor： Vasisht M. Vadi ,  Alvin Y. Ching ,  Subodh Kumar ,  Richard D. Freeman ,  Ian L. McEwen ,  Philip R. Haratsaris ,  Jaime D. Lujan ,  Eric M. Schwarz

    IPC: G06F17/50 ,  G06F9/455

    CPC classification number: G06F17/5054 ,  G06F17/5031 ,  G06F2217/84

    Abstract: A computer-implemented method of identifying timing paths of a circuit block can include representing a circuit block including at least one bypassable component as a block diagram having a plurality of elements linked by nodes. The method can include generating a map file including a text description of each element within the block diagram, wherein the text description of each element specifies a bypass indicator for the element. The method also can include generating a plurality of sub-paths from the map file, determining timing paths from the plurality of sub-paths by selectively combining different ones of the plurality of sub-paths according to commonality of starting points and ending points of the plurality of sub-paths, and outputting the timing paths.

    Abstract translation: 识别电路块的定时路径的计算机实现的方法可以包括表示包括至少一个可旁路组件的电路块作为具有由节点链接的多个元件的框图。 该方法可以包括生成包括框图中每个元素的文本描述的地图文件，其中每个元素的文本描述指定该元素的旁路指示符。 该方法还可以包括从地图文件生成多个子路径，根据多个子路径的起始点和终点的共同点选择性地组合多个子路径中的不同子路径，从多个子路径确定定时路径 多个子路径，并输出定时路径。

    METHOD FOR EXECUTING APPLICATIONS FROM A PORTABLE STORAGE DEVICE
    4.
    发明申请
    METHOD FOR EXECUTING APPLICATIONS FROM A PORTABLE STORAGE DEVICE 审中-公开
    从便携式存储设备执行应用程序的方法

    公开(公告)号：US20090319737A1

    公开(公告)日：2009-12-24

    申请号：US12440918

    申请日：2007-09-10

    Applicant: Sunder Mani ,  Subodh Kumar

    Inventor： Sunder Mani ,  Subodh Kumar

    IPC: G06F12/16 ,  G06F12/00

    CPC classification number: G06F9/44573

    Abstract: A system (10) for executing an application (30) on a computer (40) where the application (30) is stored on a portable re-writable storage device (15), the system (10) comprising: a configuration file (25) in a backup location (24) on the device (15), the configuration file (25) containing information to enable an application (30) stored on the device (15) to be executed by the computer (40), an application manager (20) to compare stored configuration files (25) on the device (15) to identify a corresponding configuration file (25) for the application (30) stored on the device (15) to be executed by the computer (40), and to read the corresponding configuration file (25) to cause the computer (40) to recognise that the application (30) was installed on the computer (40) to permit the application (30) to be executed by the computer (40).

    Abstract translation: 一种用于在计算机（40）上执行应用（30）的系统（10），其中所述应用（30）存储在便携式可重写存储设备（15）上，所述系统（10）包括：配置文件（25） ）在所述设备（15）上的备份位置（24）中，所述配置文件（25）包含用于使所述设备（15）上存储的应用（30）能够被所述计算机（40）执行的信息，应用管理器 （20）比较所述设备（15）上存储的配置文件（25），以识别由所述计算机（40）执行的存储在所述设备（15）上的所述应用（30）的相应配置文件（25）;以及 读取相应的配置文件（25），使计算机（40）识别出应用程序（30）安装在计算机（40）上，以允许计算机（40）执行应用程序（30）。

    Circuit for and method of repairing defective memory
    8.
    发明授权
    Circuit for and method of repairing defective memory 有权
    电路和修复缺陷记忆的方法

    公开(公告)号：US08103919B1

    公开(公告)日：2012-01-24

    申请号：US12359212

    申请日：2009-01-23

    Applicant: Subodh Kumar ,  Weiguang Lu

    Inventor： Subodh Kumar ,  Weiguang Lu

    IPC: G11C29/00 ,  G01R31/28

    CPC classification number: G11C29/785 ,  G11C2029/4402

    Abstract: A circuit for repairing defective memory of an integrated circuit is disclosed. The circuit includes blocks of memory; and interconnect elements providing data to each of the blocks of memory, where the interconnect elements enable coupling together the signals for programming the blocks of memory. The circuit also includes a directory of locations for defective memory cells of blocks of memory, where the directory of locations is common to the blocks of memory for storing locations of defective memory cells of the blocks of memory. Methods of repairing defective memory of an integrated circuit are also disclosed.

    Abstract translation: 公开了一种用于修复集成电路的有缺陷的存储器的电路。 该电路包括存储器块; 以及向每个存储器块提供数据的互连元件，其中互连元件使得能够将信号耦合在一起以对存储器块进行编程。 该电路还包括存储器块的缺陷存储器单元的位置目录，其中位置目录对于用于存储存储器块的缺陷存储器单元的位置的存储器块是共同的。 还公开了修复集成电路的有缺陷的存储器的方法。

    System, method, and computer program product for validating a graphics processor design
    9.
    发明授权
    System, method, and computer program product for validating a graphics processor design 有权
    用于验证图形处理器设计的系统，方法和计算机程序产品

    公开(公告)号：US08063908B1

    公开(公告)日：2011-11-22

    申请号：US11937395

    申请日：2007-11-08

    Applicant: Jonathan J. Dunaisky ,  John Malcolm Neil ,  Subodh Kumar

    Inventor： Jonathan J. Dunaisky ,  John Malcolm Neil ,  Subodh Kumar

    IPC: G06F13/14

    CPC classification number: G06T1/00

    Abstract: A system, method, and computer program product are provided for validating a graphics processor design. In operation, a test image is identified. Additionally, a reference image is automatically selected from a set of reference images. Furthermore, a graphics processor design is validated using the test image and the selected reference image.

    Abstract translation: 提供了用于验证图形处理器设计的系统，方法和计算机程序产品。 在操作中，确定测试图像。 另外，从一组参考图像中自动选择参考图像。 此外，使用测试图像和所选择的参考图像验证图形处理器设计。

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