公开(公告)号：US20100005654A1

公开(公告)日：2010-01-14

申请号：US12172079

申请日：2008-07-11

Applicant: David Hart ,  David McDonald ,  Guillaume Bouche ,  Sudarsan Uppili

Inventor： David Hart ,  David McDonald ,  Guillaume Bouche ,  Sudarsan Uppili

IPC: H05K3/02

CPC classification number: H03H3/02 ,  H03H9/175 ,  H03H9/584 ,  H03H9/589 ,  H03H2003/025 ,  Y10T29/42 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Planarization methods for maintaining planar surfaces in the fabrication of such devices as BAW devices and capacitors on a planar or planarized substrate are described. In accordance with the method, a metal layer is deposited and patterned, and an oxide layer is deposited using a high density plasma chemical vapor deposition (HDP CVD) process to a thickness equal to the thickness of the metal layer. The HDP CVD process provides an oxide layer on the patterned metal tapering upward from the edge of the patterned metal layer. Then, after masking and etching the oxide layer from the patterned metal layer, the patterned metal layer and surrounding oxide layer form a substantially planar layer, interrupted by small remaining oxide protrusions at the edges of the patterned layer. These small remaining oxide protrusions may be too small to significantly disturb the flatness of a further oxide or other layer or they may be further mitigated by the application of another HDP CVD oxide film.

Abstract translation: 描述了在平面或平面化基板上制造诸如BAW器件和电容器之类的器件的平面表面的平面化方法。 根据该方法，沉积和图案化金属层，并且使用高密度等离子体化学气相沉积（HDP CVD）工艺将氧化物层沉积到等于金属层厚度的厚度。 HDP CVD工艺在图案化金属的图案化金属层的边缘上向上逐渐变细的氧化层。 然后，在从图案化的金属层掩蔽和蚀刻氧化物层之后，图案化的金属层和周围的氧化物层形成基本平坦的层，被图案化层的边缘处的小的剩余的氧化物突起中断。 这些小的剩余氧化物突起可能太小而不能显着地扰乱另外的氧化物或其它层的平坦度，或者可以通过施加另一HDP CVD氧化物膜进一步减轻它们。

公开(公告)号：US06773973B2

公开(公告)日：2004-08-10

申请号：US09928914

申请日：2001-08-13

Applicant: Alexander Kalnitsky ,  Sudarsan Uppili ,  Sang Park

Inventor： Alexander Kalnitsky ,  Sudarsan Uppili ,  Sang Park

IPC: H01L21337

CPC classification number: H01L29/66272 ,  H01L29/7375

Abstract: A polysilicon-emitter-type transistor has a substrate with a collector region, a base region on the collector region, and an oxide layer on the base region with an emitter window therein exposing part of the base region. The polysilicon emitter is formed by forming a first polysilicon layer of approximately 30 to 100 Angstroms at least within the emitter window and at least on the exposed base region. Then, an interfacial oxide layer being approximately 5 to 50 Angstroms thick is formed in an upper portion of the first polysilicon layer, for example, by exposing the first polysilicon layer to oxygen and annealing. Then, a second polysilicon layer is formed on the interfacial oxide layer. The thickness of the second polysilicon layer may be approximately 500 to 5000 Angstroms thick. Subsequent annealing diffuses dopants in the emitter more uniformly into the base region.

Abstract translation: 多晶硅 - 发射型晶体管具有集电极区域，集电极区域上的基极区域和基极区域上的发光体窗口的氧化物层的基板，其中露出基极区域的一部分。 多晶硅发射体通过至少在发射极窗内至少在暴露的基极区上形成大约30至100埃的第一多晶硅层而形成。 然后，例如通过将第一多晶硅层暴露于氧并进行退火，在第一多晶硅层的上部形成大约5至50埃厚的界面氧化物层。 然后，在界面氧化物层上形成第二多晶硅层。 第二多晶硅层的厚度可以为约500至5000埃厚。 随后的退火将发射极中的掺杂剂更均匀地扩散到基极区域中。

公开(公告)号：US20150108429A1

公开(公告)日：2015-04-23

申请号：US14060430

申请日：2013-10-22

Applicant: Harsha Sudarsan Uppili

Inventor： Harsha Sudarsan Uppili

IPC: H01L29/12 ,  H01L29/66 ,  H01L21/02 ,  H01L29/786

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L51/0026 ,  H01L51/0048 ,  H01L51/0558

Abstract: Electronic devices include a network of purified and randomly aligned carbon nanotubes. The electronic devices include conductive regions that comprise conductive inks, and substrates such as flexible plastic materials including PET. Networks of randomly aligned carbon nanotubes are exposed to UV radiation to convert metallic carbon nanotubes to semiconductive carbon nanotubes. Conductive regions are printed onto a substrate using printing techniques such as inkjet printing and gravure printing. Devices are fabricated at low temperatures, without annealing and without vacuum.

Abstract translation: 电子器件包括纯化和随机排列的碳纳米管网络。 电子设备包括导电区域，其包括导电油墨，以及诸如包括PET的柔性塑料材料的基底。 将随机排列的碳纳米管的网络暴露于UV辐射以将金属碳纳米管转化为半导体碳纳米管。 使用诸如喷墨印刷和凹版印刷的印刷技术将导电区域印刷到基板上。 器件在低温下制造，无退火和无真空。

公开(公告)号：US08643067B2

公开(公告)日：2014-02-04

申请号：US13249529

申请日：2011-09-30

Applicant: Scott J. Alberhasky ,  David E. Hart ,  Sudarsan Uppili

Inventor： Scott J. Alberhasky ,  David E. Hart ,  Sudarsan Uppili

IPC: H01L29/66

CPC classification number: H01L29/66734 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/7802

Abstract: Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a second body region formed proximal to the first surface. Moreover, each body region includes a source region formed therein. The substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to function as a drift region between the drain region and the source regions. A dual-gate is formed over the first surface of the substrate. The dual-gate includes a first gate region and a second gate region that define a gap there between to reduce the gate to drain capacitance. A conductive layer may be formed over the first gate region and the second gate region to lower the effective resistance of the dual-gate.

Abstract translation: 描述了包括双栅极配置的半导体器件。 在一个或多个实施方案中，半导体器件包括具有第一表面和第二表面的衬底。 衬底包括靠近第一表面形成的第一和第二体区。 此外，每个体区域包括形成在其中的源极区域。 衬底还包括靠近第二表面形成的漏极区域和被配置为用作漏极区域和源极区域之间的漂移区域的外延区域。 双栅极形成在衬底的第一表面上。 双栅极包括限定其间的间隙的第一栅极区域和第二栅极区域，以减小栅极与漏极电容。 可以在第一栅极区域和第二栅极区域上形成导电层以降低双栅极的有效电阻。

公开(公告)号：USD1040992S1

公开(公告)日：2024-09-03

申请号：US29811352

申请日：2021-10-13

Applicant: Sudarsan Uppili

Designer： Jalaja V. Uppili ,  Sudarsan Uppili ,  Uppili Sridhar

Abstract: FIG. 1 is a top-front-right perspective view of a stove exhaust system showing our new design;
FIG. 2 is a front view thereof;
FIG. 3 is a back view thereof;
FIG. 4 is a right-side view thereof;
FIG. 5 is a left-side view thereof;
FIG. 6 is a top view thereof;
FIG. 7 is a bottom view thereof; and,
FIG. 8 is a top-front-left perspective view thereof.
The broken lines in FIGS. 1-6 and 8 depict portions of the stove exhaust system that form no part of the claimed design.

公开(公告)号：US20130082320A1

公开(公告)日：2013-04-04

申请号：US13249529

申请日：2011-09-30

Applicant: Scott J. Alberhasky ,  David E. Hart ,  Sudarsan Uppili

Inventor： Scott J. Alberhasky ,  David E. Hart ,  Sudarsan Uppili

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66734 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/7802

Abstract: Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a second body region formed proximal to the first surface. Moreover, each body region includes a source region formed therein. The substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to function as a drift region between the drain region and the source regions. A dual-gate is formed over the first surface of the substrate. The dual-gate includes a first gate region and a second gate region that define a gap there between to reduce the gate to drain capacitance. A conductive layer may be formed over the first gate region and the second gate region to lower the effective resistance of the dual-gate.

Abstract translation: 描述了包括双栅极配置的半导体器件。 在一个或多个实施方案中，半导体器件包括具有第一表面和第二表面的衬底。 衬底包括靠近第一表面形成的第一和第二体区。 此外，每个体区域包括形成在其中的源极区域。 衬底还包括靠近第二表面形成的漏极区域和被配置为用作漏极区域和源极区域之间的漂移区域的外延区域。 双栅极形成在衬底的第一表面上。 双栅极包括限定其间的间隙的第一栅极区域和第二栅极区域，以减小栅极与漏极电容。 可以在第一栅极区域和第二栅极区域上形成导电层以降低双栅极的有效电阻。

公开(公告)号：US09450074B1

公开(公告)日：2016-09-20

申请号：US13194210

申请日：2011-07-29

Applicant: Fanling Hsu Yang ,  Timothy K. McGuire ,  Sudarsan Uppili ,  Guillaume Bouche

Inventor： Fanling Hsu Yang ,  Timothy K. McGuire ,  Sudarsan Uppili ,  Guillaume Bouche

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66681 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7824 ,  H01L29/7835

Abstract: Semiconductor devices, such as laterally diffused metal oxide semiconductor (LDMOS) devices, are described that have a field plate connected to a gate of the device. In one or more implementations, the semiconductor devices include a substrate having a source region of a first conductivity type and a drain region of the first conductivity type. A gate is positioned over the surface and between the source region and the drain region. The gate is configured to receive a voltage so that a conduction region may be formed at least partially below the gate to allow majority carriers to travel between the source region and the drain region. The device also includes a field plate at least partially positioned over and connected to the gate. The field plate is configured to shape an electrical field generated between the source region and the drain region when a voltage is applied to the gate.

Abstract translation: 描述了半导体器件，例如横向扩散的金属氧化物半导体（LDMOS）器件，其具有连接到器件的栅极的场板。 在一个或多个实施方案中，半导体器件包括具有第一导电类型的源极区和第一导电类型的漏极区的衬底。 栅极位于表面上并且在源极区域和漏极区域之间。 栅极被配置为接收电压，使得可以至少部分地在栅极下方形成导电区域，以允许多数载流子在源极区域和漏极区域之间行进。 该装置还包括至少部分地定位在栅极上并连接到栅极的场板。 场板被配置为当电压施加到栅极时，使在源极区域和漏极区域之间产生的电场成形。

公开(公告)号：US09171916B1

公开(公告)日：2015-10-27

申请号：US13272301

申请日：2011-10-13

Applicant: David L. Snyder ,  Sudarsan Uppili ,  Guillaume Bouche

Inventor： David L. Snyder ,  Sudarsan Uppili ,  Guillaume Bouche

IPC: H01L29/40 ,  H01L21/8238

CPC classification number: H01L29/402 ,  H01L21/82385 ,  H01L29/063 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: Semiconductor devices, such as LDMOS devices, are described that include an interlayer-dielectric layer (ILD) region having a thickness of at least two and one half (2.5) microns to increase the maximum breakdown voltage. In one or more implementations, the semiconductor devices include a substrate having a source region and a drain region formed proximate to a surface of the substrate. A gate is positioned over the surface and between the source region and the drain region. An ILD region having a thickness of at least two and one half (2.5) microns is formed over the surface and the gate of the device. The device also includes one or more field plates configured to shape an electrical field generated between the source region and the drain region when a voltage is applied to the gate.

Abstract translation: 描述了诸如LDMOS器件的半导体器件，其包括具有至少两个和一个（2.5）微米厚度的层间介电层（ILD）区域以增加最大击穿电压。 在一个或多个实施方案中，半导体器件包括具有靠近衬底表面形成的源区和漏区的衬底。 栅极位于表面上并且在源极区域和漏极区域之间。 在器件的表面和栅极上形成具有至少两个半（2.5）微米厚度的ILD区域。 该装置还包括一个或多个场板，其配置成当电压施加到栅极时，使在源极区域和漏极区域之间产生的电场成形。

公开(公告)号：US09209091B1

公开(公告)日：2015-12-08

申请号：US13198833

申请日：2011-08-05

Applicant: David Harper ,  Sudarsan Uppili ,  Fanling Hsu Yang ,  David L. Snyder ,  Christopher S. Blair ,  Guillaume Bouche

Inventor： David Harper ,  Sudarsan Uppili ,  Fanling Hsu Yang ,  David L. Snyder ,  Christopher S. Blair ,  Guillaume Bouche

IPC: H01L21/00 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L27/1211

Abstract: A semiconductor device is described that includes a first electrical circuit and a second electrical circuit formed on a semiconductor on insulator wafer. The semiconductor on insulator wafer has a layer of semiconducting material formed over a buried layer of insulating material formed over a supporting layer of material. A wide deep trench is formed in the semiconductor on insulator wafer to galvanically isolate the first electrical circuit from the second electrical circuit. The first electrical circuit and the second electrical circuit are coupled together for exchanging energy between the galvanically isolated electrical circuits.

Abstract translation: 描述了包括形成在绝缘体上半导体晶片上的第一电路和第二电路的半导体器件。 绝缘体上半导体晶片具有形成在绝缘材料的掩埋层上的半导体材料层，其形成在材料的支撑层上。 在半导体绝缘体晶片上形成宽的深沟槽，以将第一电路与第二电路电隔离。 第一电路和第二电路耦合在一起，用于在电隔离的电路之间交换能量。

公开(公告)号：US07966722B2

公开(公告)日：2011-06-28

申请号：US12172079

申请日：2008-07-11

Applicant: David Hart ,  David McDonald ,  Guillaume Bouche ,  Sudarsan Uppili

Inventor： David Hart ,  David McDonald ,  Guillaume Bouche ,  Sudarsan Uppili

IPC: H05K3/02

CPC classification number: H03H3/02 ,  H03H9/175 ,  H03H9/584 ,  H03H9/589 ,  H03H2003/025 ,  Y10T29/42 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Planarization methods for maintaining planar surfaces in the fabrication of such devices as BAW devices and capacitors on a planar or planarized substrate are described. In accordance with the method, a metal layer is deposited and patterned, and an oxide layer is deposited using a high density plasma chemical vapor deposition (HDP CVD) process to a thickness equal to the thickness of the metal layer. The HDP CVD process provides an oxide layer on the patterned metal tapering upward from the edge of the patterned metal layer. Then, after masking and etching the oxide layer from the patterned metal layer, the patterned metal layer and surrounding oxide layer form a substantially planar layer, interrupted by small remaining oxide protrusions at the edges of the patterned layer. These small remaining oxide protrusions may be too small to significantly disturb the flatness of a further oxide or other layer or they may be further mitigated by the application of another HDP CVD oxide film.

Abstract translation: 描述了在平面或平面化基板上制造诸如BAW器件和电容器之类的器件的平面表面的平面化方法。 根据该方法，沉积和图案化金属层，并且使用高密度等离子体化学气相沉积（HDP CVD）工艺将氧化物层沉积到厚度等于金属层的厚度。 HDP CVD工艺在图案化金属的图案化金属层的边缘上向上逐渐变细的氧化层。 然后，在从图案化的金属层掩蔽和蚀刻氧化物层之后，图案化的金属层和周围的氧化物层形成基本平坦的层，被图案化层的边缘处的小的剩余的氧化物突起中断。 这些小的剩余氧化物突起可能太小而不能显着地扰乱另外的氧化物或其它层的平坦度，或者可以通过施加另一HDP CVD氧化物膜进一步减轻它们。