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    COMPACT, LOW POWER ADVANCED ENCRYPTION STANDARD CIRCUIT
    1.
    发明申请
    COMPACT, LOW POWER ADVANCED ENCRYPTION STANDARD CIRCUIT 有权
    紧凑型低功耗高级加密标准电路

    公开(公告)号：US20150086007A1

    公开(公告)日：2015-03-26

    申请号：US14035508

    申请日：2013-09-24

    Applicant: Sanu MATHEW ,  Vikram Suresh ,  Sudhir Satpathy ,  Mark Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

    Inventor： Sanu MATHEW ,  Vikram Suresh ,  Sudhir Satpathy ,  Mark Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

    IPC: H04L9/30

    CPC classification number: H04L9/0631 ,  H04L2209/24

    Abstract: Embodiments of an invention for a compact, low power Advanced Encryption Standard circuit are disclosed. In one embodiment, an apparatus includes an encryption unit having a substitution box and an accumulator. The substitution box is to perform a substitution operation on one byte per clock cycle. The accumulator is to accumulate four bytes and perform a mix-column operation in four clock cycles. The encryption unit is implemented using optimum Galois Field polynomial arithmetic for minimum area.

    Abstract translation: 公开了一种用于紧凑型低功率高级加密标准电路的发明的实施例。 在一个实施例中，装置包括具有替换盒和累加器的加密单元。 替代方案是对每个时钟周期的一个字节执行替换操作。 累加器将累积四个字节，并在四个时钟周期内执行混合列操作。 加密单元使用最小区域的最优伽罗瓦域多项式运算来实现。

    HARDWARE ACCELERATORS AND METHODS FOR HIGH-PERFORMANCE AUTHENTICATED ENCRYPTION
    3.
    发明申请
    HARDWARE ACCELERATORS AND METHODS FOR HIGH-PERFORMANCE AUTHENTICATED ENCRYPTION 审中-公开

    公开(公告)号：US20190042249A1

    公开(公告)日：2019-02-07

    申请号：US15943654

    申请日：2018-04-02

    Applicant: VIKRAM SURESH ,  SANU MATHEW ,  SUDHIR SATPATHY ,  VINODH GOPAL

    Inventor： VIKRAM SURESH ,  SANU MATHEW ,  SUDHIR SATPATHY ,  VINODH GOPAL

    IPC: G06F9/30 ,  G06F9/38 ,  H04L9/06

    Abstract: Methods and apparatuses relating to high-performance authenticated encryption are described. A hardware accelerator may include a vector register to store an input vector of a round of an encryption operation; a circuit including a first data path including a first modular adder coupled to a first input from the vector register and a second input from the vector register, and a second modular adder coupled to the first modular adder and a second data path from the vector register, and the second data path including a first logical XOR circuit coupled to the second input and a third data path from the vector register, a first rotate circuit coupled to the first logical XOR circuit, a second logical XOR circuit coupled to the first rotate circuit and the third data path, and a second rotate circuit coupled to the second logical XOR circuit; and a control circuit to cause the first modular adder and the second modular adder of the first data path and the first logical XOR circuit, the second logical XOR circuit, the first rotate circuit, and the second rotate circuit of the second data path to perform a portion of the round according to one or more control values, and store a first result from the first data path for the portion and a second result from the second data path for the portion into the vector register.

    PRIORITY-BASED ROUTING
    5.
    发明申请
    PRIORITY-BASED ROUTING 有权
    优先级路由

    公开(公告)号：US20150188829A1

    公开(公告)日：2015-07-02

    申请号：US14141356

    申请日：2013-12-26

    Applicant: Sudhir Satpathy ,  Himanshu Kaul ,  Mark Anders ,  Sanu Mathew ,  Gregory Chen ,  Ram Krishnamurthy

    Inventor： Sudhir Satpathy ,  Himanshu Kaul ,  Mark Anders ,  Sanu Mathew ,  Gregory Chen ,  Ram Krishnamurthy

    IPC: H04L12/833 ,  H04L12/933 ,  H04L12/725

    CPC classification number: H04L47/2458 ,  H04L45/30 ,  H04L47/56 ,  H04L47/6275 ,  H04L49/109

    Abstract: Disclosed herein is a router configured for priority-based routing. The router is configured to receive a plurality of packets, wherein each packet is assigned a priority value. The router includes an output circuit configured to select the packet with the highest priority value. The output circuit is configured to forward the priority value of the selected packet to a second router. The output circuit is configured to transfer the selected packet to the second router when the link between the first router and the second router is available.

    Abstract translation: 这里公开了配置用于基于优先级路由的路由器。 路由器被配置为接收多个分组，其中每个分组被分配优先级值。 路由器包括配置为选择具有最高优先级值的分组的输出电路。 输出电路被配置为将所选择的分组的优先级值转发给第二路由器。 输出电路被配置为当第一路由器和第二路由器之间的链路可用时将所选择的分组传送到第二路由器。

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