公开(公告)号：US20120081645A1

公开(公告)日：2012-04-05

申请号：US13170804

申请日：2011-06-28

Applicant: Tetsuo Yoshimura ,  Michihiro Onoda

Inventor： Tetsuo Yoshimura ,  Michihiro Onoda

IPC: G02F1/1335 ,  H01J9/24

CPC classification number: G02F1/136209 ,  G02F1/136227 ,  G02F1/136277

Abstract: Above a semiconductor substrate on which switching semiconductor elements are formed respectively corresponding to a plurality of pixels, a first and a second copper wiring layers and thereon an aluminum reflection electrode layer are arranged. Wirings and first and second light shielding layers are formed by patterning the copper wiring layers and pluralities of first and second openings are formed respectively in the first and the second light shielding layers. The first openings and the second openings are shifted in two directions not to overlap each other in a plan view. The wiring layers and the light shielding layers are formed of copper while restraining dishing.

Abstract translation: 在分别对应于多个像素的半导体衬底上形成有开关半导体元件的第一和第二铜布线层和铝反射电极层之上。 布线和第一和第二遮光层通过图案化铜布线层而形成，并且多个第一和第二开口分别形成在第一和第二遮光层中。 第一开口和第二开口在平面图中在彼此不重叠的两个方向上移动。 布线层和遮光层由铜形成，同时抑制凹陷。

公开(公告)号：US07005755B2

公开(公告)日：2006-02-28

申请号：US10745645

申请日：2003-12-29

Applicant: Tetsuo Yoshimura ,  Shinji Kuzuya ,  Kazuo Sukegawa ,  Tetsuo Izawa

Inventor： Tetsuo Yoshimura ,  Shinji Kuzuya ,  Kazuo Sukegawa ,  Tetsuo Izawa

IPC: H01L23/544

CPC classification number: H01L21/76283 ,  H01L21/76264 ,  H01L23/544 ,  H01L27/1203 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device formed on a SOI substrate includes isolation trenches formed in a first region and reaching an insulation layer buried in the SOI substrate, and alignment marks formed in a second region and consisting of grooves extending into a support substrate.

公开(公告)号：US20120190154A1

公开(公告)日：2012-07-26

申请号：US13434177

申请日：2012-03-29

Applicant: Tetsuo Yoshimura ,  Kenichi Watanabe ,  Satoshi Otsuka

Inventor： Tetsuo Yoshimura ,  Kenichi Watanabe ,  Satoshi Otsuka

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01G4/005 ,  H01G4/228 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, an insulating film formed over the substrate, first and second conductive plugs formed in the insulating film, a capacitor element, and a wiring. The capacitor element includes a lower electrode, a dielectric film, and an upper electrode. The lower electrode is connected to an end of the first plug and formed on the insulating film, and includes a first barrier film. The dielectric film is formed on upper and side surfaces of the lower electrode. The upper electrode is formed on the dielectric film, and includes a second barrier metal film being wider than the lower electrode. The wiring is connected to an end of the second plug and formed on the insulating film, and includes a first layer and a second layer formed on the first layer. The first and second layers include the first and second barrier metal films, respectively.

Abstract translation: 半导体器件包括衬底，在衬底上形成的绝缘膜，形成在绝缘膜中的第一和第二导电插塞，电容器元件和布线。 电容器元件包括下电极，电介质膜和上电极。 下电极连接到第一插头的端部并形成在绝缘膜上，并且包括第一阻挡膜。 电介质膜形成在下电极的上表面和侧表面上。 上电极形成在电介质膜上，并且包括比下电极宽的第二阻挡金属膜。 布线连接到第二插头的端部并形成在绝缘膜上，并且包括形成在第一层上的第一层和第二层。 第一层和第二层分别包括第一和第二阻挡金属膜。

公开(公告)号：US08169051B2

公开(公告)日：2012-05-01

申请号：US12539723

申请日：2009-08-12

Applicant: Tetsuo Yoshimura ,  Kenichi Watanabe ,  Satoshi Otsuka

Inventor： Tetsuo Yoshimura ,  Kenichi Watanabe ,  Satoshi Otsuka

IPC: H01L29/92

CPC classification number: H01G4/005 ,  H01G4/228 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, an insulating film formed over the substrate, first and second conductive plugs formed in the insulating film, a capacitor element, and a wiring. The capacitor element includes a lower electrode, a dielectric film, and an upper electrode. The lower electrode is connected to an end of the first plug and formed on the insulating film, and includes a first barrier film. The dielectric film is formed on upper and side surfaces of the lower electrode. The upper electrode is formed on the dielectric film, and includes a second barrier metal film being wider than the lower electrode. The wiring is connected to an end of the second plug and formed on the insulating film, and includes a first layer and a second layer formed on the first layer. The first and second layers include the first and second barrier metal films, respectively.

Abstract translation: 半导体器件包括衬底，在衬底上形成的绝缘膜，形成在绝缘膜中的第一和第二导电插塞，电容器元件和布线。 电容器元件包括下电极，电介质膜和上电极。 下电极连接到第一插头的端部并形成在绝缘膜上，并且包括第一阻挡膜。 电介质膜形成在下电极的上表面和侧表面上。 上电极形成在电介质膜上，并且包括比下电极宽的第二阻挡金属膜。 布线连接到第二插头的端部并形成在绝缘膜上，并且包括形成在第一层上的第一层和第二层。 第一层和第二层分别包括第一和第二阻挡金属膜。

公开(公告)号：US20050282386A1

公开(公告)日：2005-12-22

申请号：US10973440

申请日：2004-10-27

Applicant: Tetsuo Yoshimura

Inventor： Tetsuo Yoshimura

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/823871 ,  H01L21/76895 ,  H01L21/823835

Abstract: A semiconductor device includes a substrate having first and second device regions separated from each other by a device isolation region, a first field effect transistor having a first polysilicon gate electrode and formed in the first device region, a second field effect transistor having a second polysilicon gate electrode and formed in the second device region, a polysilicon pattern extending over the device isolation region from the first polysilicon gate electrode to the second polysilicon gate electrode, and a silicide layer formed on a surface of the first polysilicon gate electrode, a surface of said the polysilicon gate electrode and a surface of the polysilicon pattern so as to extend on the polysilicon pattern from the first polysilicon gate electrode to the second polysilicon gate electrode, the silicide layer having a region of increased film thickness on the polysilicon pattern, wherein the silicide layer has a surface protruding upward in the region of increased film thickness.

Abstract translation: 半导体器件包括具有通过器件隔离区彼此分离的第一和第二器件区的衬底，具有第一多晶硅栅电极并形成在第一器件区中的第一场效应晶体管，具有第二多晶硅的第二场效应晶体管， 并且形成在所述第二器件区域中的多晶硅图案，在所述器件隔离区域上延伸从所述第一多晶硅栅电极到所述第二多晶硅栅电极的多晶硅图案，以及形成在所述第一多晶硅栅电极的表面上的硅化物层， 所述多晶硅栅电极和所述多晶硅图案的表面，以便在所述多晶硅图案上从所述第一多晶硅栅电极延伸到所述第二多晶硅栅电极，所述硅化物层具有在所述多晶硅图案上增加膜厚度的区域，其中， 硅化物层在膜增加的区域中具有向上突出的表面 小心

公开(公告)号：US20090294902A1

公开(公告)日：2009-12-03

申请号：US12539723

申请日：2009-08-12

Applicant: Tetsuo Yoshimura ,  Kenichi Watanabe ,  Satoshi Otsuka

Inventor： Tetsuo Yoshimura ,  Kenichi Watanabe ,  Satoshi Otsuka

IPC: H01L29/92 ,  H01L23/525 ,  H01L21/02

CPC classification number: H01G4/005 ,  H01G4/228 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, an insulating film formed over the substrate, first and second conductive plugs formed in the insulating film, a capacitor element, and a wiring. The capacitor element includes a lower electrode, a dielectric film, and an upper electrode. The lower electrode is connected to an end of the first plug and formed on the insulating film, and includes a first barrier film. The dielectric film is formed on upper and side surfaces of the lower electrode. The upper electrode is formed on the dielectric film, and includes a second barrier metal film being wider than the lower electrode. The wiring is connected to an end of the second plug and formed on the insulating film, and includes a first layer and a second layer formed on the first layer. The first and second layers include the first and second barrier metal films, respectively.

Abstract translation: 半导体器件包括衬底，在衬底上形成的绝缘膜，形成在绝缘膜中的第一和第二导电插塞，电容器元件和布线。 电容器元件包括下电极，电介质膜和上电极。 下电极连接到第一插头的端部并形成在绝缘膜上，并且包括第一阻挡膜。 电介质膜形成在下电极的上表面和侧表面上。 上电极形成在电介质膜上，并且包括比下电极宽的第二阻挡金属膜。 布线连接到第二插头的端部并形成在绝缘膜上，并且包括形成在第一层上的第一层和第二层。 第一层和第二层分别包括第一和第二阻挡金属膜。

公开(公告)号：US06706610B2

公开(公告)日：2004-03-16

申请号：US10231046

申请日：2002-08-30

Applicant: Tetsuo Yoshimura ,  Shinji Kuzuya ,  Kazuo Sukegawa ,  Tetsuo Izawa

Inventor： Tetsuo Yoshimura ,  Shinji Kuzuya ,  Kazuo Sukegawa ,  Tetsuo Izawa

IPC: H01L2176

CPC classification number: H01L21/76283 ,  H01L21/76264 ,  H01L23/544 ,  H01L27/1203 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device formed on a SOI substrate includes isolation trenches formed in a first region and reaching an insulation layer buried in the SOI substrate, and alignment marks formed in a second region and consisting of grooves extending into a support substrate.

Abstract translation: 形成在SOI衬底上的半导体器件包括形成在第一区域中并到达掩埋在SOI衬底中的绝缘层的隔离沟槽，以及形成在第二区域中并由延伸到支撑衬底中的沟槽组成的对准标记。

公开(公告)号：US08642400B2

公开(公告)日：2014-02-04

申请号：US13434177

申请日：2012-03-29

Applicant: Tetsuo Yoshimura ,  Kenichi Watanabe ,  Satoshi Otsuka

Inventor： Tetsuo Yoshimura ,  Kenichi Watanabe ,  Satoshi Otsuka

IPC: H01L21/20

CPC classification number: H01G4/005 ,  H01G4/228 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device includes: forming a first metal film on an insulating film over a substrate; forming a capacitor lower electrode by patterning the first metal film; and forming a dielectric film on upper and side surfaces of the capacitor lower electrode and on the insulating film. The method further includes: forming a conductive protection film on the dielectric film; patterning the conductive protection film into a shape of covering the capacitor lower electrode; forming a capacitor dielectric film in a shape of covering the upper and side surfaces of the capacitor lower electrode, by patterning the dielectric film so that the patterned conductive protection film covers an upper surface of the capacitor dielectric film; forming a second metal film on the patterned conductive protection film; and forming a capacitor upper electrode that covers at least an upper surface of the patterned conductive protection film.

Abstract translation: 一种制造半导体器件的方法包括：在衬底上的绝缘膜上形成第一金属膜; 通过图案化第一金属膜形成电容器下电极; 并且在电容器下电极的上表面和侧表面上以及绝缘膜上形成电介质膜。 该方法还包括：在电介质膜上形成导电保护膜; 将导电保护膜图案化成覆盖电容器下电极的形状; 通过对所述电介质膜进行构图来形成覆盖所述电容器下电极的上表面和所述侧表面的电容器电介质膜，使得所述图案化的导电保护膜覆盖所述电容器电介质膜的上表面; 在图案化的导电保护膜上形成第二金属膜; 以及形成覆盖图案化的导电保护膜的至少上表面的电容器上电极。

公开(公告)号：US20120140151A1

公开(公告)日：2012-06-07

申请号：US13321033

申请日：2010-01-27

Applicant: Tetsuo Yoshimura ,  Eiichiroh Nishimura

Inventor： Tetsuo Yoshimura ,  Eiichiroh Nishimura

IPC: G02F1/1335

CPC classification number: G02B5/3041 ,  G02F1/13338 ,  G02F1/133528 ,  G02F2202/28 ,  G06F3/041

Abstract: A liquid crystal panel 10, a multilayer polarization plate 20, and a cover member such as a touch panel 30, a cover glass, or the like are laminated in this order to form a liquid crystal display device 1. The multilayer polarization plate 20 and the liquid crystal panel 10 are attached together by an adhesive layer 24 formed on one surface of the multilayer polarization plate 20. The multilayer polarizing plate 20 and the cover member are attached together by an adhesive layer 26 formed on the other surface of the multilayer polarization plate 20. The adhesive layers 24 and 26 are respectively covered by separators 25 and 27.

Abstract translation: 依次层叠液晶面板10，多层偏振板20以及触摸面板30，盖玻璃等覆盖部件，形成液晶显示装置1.多层偏光板20和 液晶板10通过形成在多层偏振板20的一个表面上的粘合剂层24附着在一起。多层偏光板20和盖构件通过形成在多层偏振片20的另一表面上的粘合剂层26附着在一起 粘合剂层24和26分别被隔板25和27覆盖。

公开(公告)号：US07326648B2

公开(公告)日：2008-02-05

申请号：US11602241

申请日：2006-11-21

Applicant: Tetsuo Yoshimura

Inventor： Tetsuo Yoshimura

IPC: H01L21/44

CPC classification number: H01L21/823871 ,  H01L21/76895 ,  H01L21/823835

Abstract: A semiconductor device includes a substrate having first and second device regions separated from each other by a device isolation region, a first field effect transistor having a first polysilicon gate electrode and formed in the first device region, a second field effect transistor having a second polysilicon gate electrode and formed in the second device region, a polysilicon pattern extending over the device isolation region from the first polysilicon gate electrode to the second polysilicon gate electrode, and a silicide layer formed on a surface of the first polysilicon gate electrode, a surface of said the polysilicon gate electrode and a surface of the polysilicon pattern so as to extend on the polysilicon pattern from the first polysilicon gate electrode to the second polysilicon gate electrode, the silicide layer having a region of increased film thickness on the polysilicon pattern, wherein the silicide layer has a surface protruding upward in the region of increased film thickness.

Abstract translation: 半导体器件包括具有通过器件隔离区彼此分离的第一和第二器件区的衬底，具有第一多晶硅栅电极并形成在第一器件区中的第一场效应晶体管，具有第二多晶硅的第二场效应晶体管， 并且形成在所述第二器件区域中的多晶硅图案，在所述器件隔离区域上延伸从所述第一多晶硅栅电极到所述第二多晶硅栅电极的多晶硅图案，以及形成在所述第一多晶硅栅电极的表面上的硅化物层， 所述多晶硅栅电极和所述多晶硅图案的表面，以便在所述多晶硅图案上从所述第一多晶硅栅电极延伸到所述第二多晶硅栅电极，所述硅化物层具有在所述多晶硅图案上增加膜厚度的区域，其中， 硅化物层在膜增加的区域中具有向上突出的表面 小心