公开(公告)号：US09727528B2

公开(公告)日：2017-08-08

申请号：US13178062

申请日：2011-07-07

Applicant: Bernhard Egger ,  Taisong Jin ,  Won-Sub Kim

Inventor： Bernhard Egger ,  Taisong Jin ,  Won-Sub Kim

IPC: G06F15/78 ,  G06F9/38

CPC classification number: G06F15/7892 ,  G06F9/3869

Abstract: Provided is a reconfigurable processor capable of reducing the routing processing time of routing nodes by driving the routing nodes at a greater frequency than a driving frequency of the processing elements. The reconfigurable processor includes one or more processing elements configured to be driven at a first driving frequency, and one or more routing nodes configured to be provided on paths that are formed between the processing elements, and to be driven at a second driving frequency that is greater than the first driving frequency.

公开(公告)号：US08930929B2

公开(公告)日：2015-01-06

申请号：US13086629

申请日：2011-04-14

Applicant: Min-Wook Ahn ,  Dong-Hoon Yoo ,  Jin-Seok Lee ,  Bernhard Egger ,  Tai-Song Jin ,  Won-Sub Kim ,  Hee-Jin Ahn

Inventor： Min-Wook Ahn ,  Dong-Hoon Yoo ,  Jin-Seok Lee ,  Bernhard Egger ,  Tai-Song Jin ,  Won-Sub Kim ,  Hee-Jin Ahn

IPC: G06F9/45 ,  G06F9/50

CPC classification number: G06F9/5066

Abstract: A reconfigurable processor which merges an inner loop and an outer loop which are included in a nested loop and allocates the merged loop to processing elements in parallel, thereby reducing processing time to process the nested loop. The reconfigurable processor may extract loop execution frequency information from the inner loop and the outer loop of the nested loop, and may merge the inner loop and the outer loop based on the extracted loop execution frequency information.

Abstract translation: 一种可重构的处理器，它将包含在嵌套循环中的内循环和外循环合并，并行地将合并循环分配给处理元素，从而减少了处理嵌套循环的处理时间。 可重配置处理器可以从嵌套循环的内循环和外循环提取循环执行频率信息，并且可以基于提取的循环执行频率信息合并内循环和外循环。

公开(公告)号：US08745608B2

公开(公告)日：2014-06-03

申请号：US12697602

申请日：2010-02-01

Applicant: Won-sub Kim ,  Tae-wook Oh ,  Bernhard Egger

Inventor： Won-sub Kim ,  Tae-wook Oh ,  Bernhard Egger

IPC: G06F9/45

CPC classification number: G06F9/3897 ,  G06F9/3838

Abstract: A scheduler of a reconfigurable array, a method of scheduling commands, and a computing apparatus are provided. To perform a loop operation in a reconfigurable array, a recurrence node, a producer node, and a predecessor node are detected from a data flow graph of the loop operation such that resources are assigned to such nodes so as to increase the loop operating speed. Also, a dedicated path having a fixed delay may be added to the assigned resources.

Abstract translation: 提供了可重配置阵列的调度器，调度命令的方法和计算装置。 为了在可重配置阵列中执行循环操作，从循环操作的数据流图中检测到递归节点，生成器节点和前导节点，使得资源被分配给这样的节点，以便增加循环操作速度。 此外，具有固定延迟的专用路径可以被添加到所分配的资源。

公开(公告)号：US20130124839A1

公开(公告)日：2013-05-16

申请号：US13585221

申请日：2012-08-14

Applicant: Min-Wook AHN ,  Won-Sub Kim ,  Dong-Hoon Yoo

Inventor： Min-Wook AHN ,  Won-Sub Kim ,  Dong-Hoon Yoo

IPC: G06F9/38

CPC classification number: G06F8/4452

Abstract: A technology for executing an external operation from a software-pipelined loop is provided. Code performance efficiency can be improved by overlapping the execution of the external operations of the loop and the iterations of the loop.

Abstract translation: 提供了一种从软件流水线循环执行外部操作的技术。 通过重复执行循环的外部操作和循环的迭代可以提高代码性能效率。

公开(公告)号：US20120204001A1

公开(公告)日：2012-08-09

申请号：US13178062

申请日：2011-07-07

Applicant: Bernhard Egger ,  Taisong Jin ,  Won-Sub Kim

Inventor： Bernhard Egger ,  Taisong Jin ,  Won-Sub Kim

IPC: G06F15/76 ,  G06F9/06

CPC classification number: G06F15/7892 ,  G06F9/3869

Abstract: Provided is a reconfigurable processor capable of reducing the routing processing time of routing nodes by driving the routing nodes at a greater frequency than a driving frequency of the processing elements. The reconfigurable processor includes one or more processing elements configured to be driven at a first driving frequency, and one or more routing nodes configured to be provided on paths that are formed between the processing elements, and to be driven at a second driving frequency that is greater than the first driving frequency.

Abstract translation: 提供了一种可重新配置的处理器，其能够以比处理元件的驱动频率更大的频率驱动路由节点来减少路由节点的路由处理时间。 可重配置处理器包括被配置为以第一驱动频率驱动的一个或多个处理元件，以及一个或多个路由节点，被配置为提供在形成在处理元件之间的路径上，并以第二驱动频率 大于第一驱动频率。

公开(公告)号：US20120185673A1

公开(公告)日：2012-07-19

申请号：US13213333

申请日：2011-08-19

Applicant: Sung-Joo Yoo ,  Yeon-Gon Cho ,  Bernhard Egger ,  Won-Sub Kim ,  Hee-Jin Ahn

Inventor： Sung-Joo Yoo ,  Yeon-Gon Cho ,  Bernhard Egger ,  Won-Sub Kim ,  Hee-Jin Ahn

IPC: G06F15/80 ,  G06F1/26 ,  G06F9/02

CPC classification number: G06F15/7867 ,  G06F1/3287 ,  G06F8/4432 ,  G06F8/447 ,  G06F9/30083 ,  G06F9/30189 ,  G06F9/3889 ,  Y02D10/171 ,  Y02D50/20

Abstract: Provided is a reconfigurable processor that may process a first type of operation in first mode using a first group of functional units, and process a second type of operation in second mode using a second group of functional units. The reconfigurable processor may selectively supply power to either the first group or the second group, in response to a mode-switch signal or a mode-switch instruction.

Abstract translation: 提供了一种可重构处理器，其可以使用第一组功能单元处理第一模式中的第一类型的操作，并且使用第二组功能单元处理第二模式中的第二类型的操作。 可重新配置的处理器可以响应于模式切换信号或模式切换指令而选择性地向第一组或第二组提供电力。

公开(公告)号：US20110231627A1

公开(公告)日：2011-09-22

申请号：US12917173

申请日：2010-11-01

Applicant: Bernhard EGGER ,  Tai-Song Jin ,  Dong-Hoon Yoo ,  Won-Sub Kim ,  Sun-Hwa Kim ,  Hee-Jin Ahn

Inventor： Bernhard EGGER ,  Tai-Song Jin ,  Dong-Hoon Yoo ,  Won-Sub Kim ,  Sun-Hwa Kim ,  Hee-Jin Ahn

IPC: G06F12/02 ,  G06F12/00

CPC classification number: G06F12/0253

Abstract: A memory managing apparatus and method are provided. The memory managing apparatus may determine, based on a pointer indicator bit, the target memory area on which garbage collection is to be performed, and may perform the garbage collection on the target memory area. The memory managing apparatus may generate the pointer indicator bit and store the generated pointer indicator bit in a pointer field.

Abstract translation: 提供了一种存储器管理装置和方法。 存储器管理装置可以基于指针指示符位来确定要在其上执行垃圾收集的目标存储器区域，并且可以在目标存储器区域上执行垃圾收集。 存储器管理装置可以生成指针指示符位，并将生成的指针指示符位存储在指针字段中。

公开(公告)号：US20110225399A1

公开(公告)日：2011-09-15

申请号：US12964377

申请日：2010-12-09

Applicant: Tai-Song JIN ,  Dong-Hoon Yoo ,  Bernhard Egger ,  Won-Sub Kim

Inventor： Tai-Song JIN ,  Dong-Hoon Yoo ,  Bernhard Egger ,  Won-Sub Kim

IPC: G06F9/30

CPC classification number: G06F9/30065 ,  G06F9/3001 ,  G06F9/3893

Abstract: A processor for supporting a MIMO operation and method of processing a MIMO instruction are provided. The MIMO operation supporting processor may include a scheduler and at least one functional unit. The scheduler may map multiple inputs of the MIMO instruction to a plurality of sequential input cycles, respectively, and may map multiple outputs of the MIMO instruction to a plurality of sequential output cycles, respectively. The output cycles may be followed by the input cycles and a predetermined number of cycles for a MIMO operation. A functional unit may read a register during sequential input cycles, may perform a MIMO operation during a predetermined number of execution cycles, and may write the result of the MIMO operation into a register during sequential output cycles.

Abstract translation: 提供了一种用于支持MIMO操作的处理器和处理MIMO指令的方法。 MIMO操作支持处理器可以包括调度器和至少一个功能单元。 调度器可以将MIMO指令的多个输入分别映射到多个顺序输入周期，并且可以将MIMO指令的多个输出分别映射到多个顺序输出周期。 输出周期之后可以是用于MIMO操作的输入周期和预定数量的周期。 功能单元可以在顺序输入周期期间读取寄存器，可以在预定数量的执行周期内执行MIMO操作，并且可以在顺序输出周期期间将MIMO操作的结果写入寄存器。

公开(公告)号：US09063735B2

公开(公告)日：2015-06-23

申请号：US13272846

申请日：2011-10-13

Applicant: Hee-Jin Ahn ,  Dong-Hoon Yoo ,  Bernhard Egger ,  Min-Wook Ahn ,  Jin-Seok Lee ,  Tai-Song Jin ,  Won-Sub Kim

Inventor： Hee-Jin Ahn ,  Dong-Hoon Yoo ,  Bernhard Egger ,  Min-Wook Ahn ,  Jin-Seok Lee ,  Tai-Song Jin ,  Won-Sub Kim

IPC: G06F9/38 ,  G06F9/32

CPC classification number: G06F9/325 ,  G06F9/3838 ,  G06F9/3897

Abstract: Provided are a reconfigurable processor, which is capable of reducing the probability of an incorrect computation by analyzing the dependence between memory access instructions and allocating the memory access instructions between a plurality of processing elements (PEs) based on the results of the analysis, and a method of controlling the reconfigurable processor. The reconfigurable processor extracts an execution trace from simulation results, and analyzes the memory dependence between instructions included in different iterations based on parts of the execution trace of memory access instructions.

Abstract translation: 提供了一种可重构处理器，其能够通过分析存储器访问指令之间的依赖性并且基于分析结果在多个处理元件（PE）之间分配存储器访问指令，从而降低错误计算的概率，以及 控制可重构处理器的方法。 可重配置处理器从模拟结果中提取执行跟踪，并且基于存储器访问指令的执行跟踪的部分来分析包括在不同迭代中的指令之间的存储器依赖性。

公开(公告)号：US08869129B2

公开(公告)日：2014-10-21

申请号：US12610571

申请日：2009-11-02

Applicant: Tae-wook Oh ,  Won-sub Kim ,  Bernhard Egger

Inventor： Tae-wook Oh ,  Won-sub Kim ,  Bernhard Egger

IPC: G06F9/45 ,  G06F7/00

CPC classification number: G06F8/451

Abstract: An apparatus and method for scheduling an instruction are provided. The apparatus includes an analyzer configured to analyze dependency of a plurality of recurrence loops and a scheduler configured to schedule the recurrence loops based the analyzed dependencies. When scheduling a plurality of recurrence loops, the apparatus first schedules a dominant loop whose loop head has no dependency on another loop among the recurrence loops.

Abstract translation: 提供了一种用于调度指令的装置和方法。 该装置包括分析器，其被配置为分析多个循环循环的依赖性，以及调度器，其被配置为基于所分析的依赖性来调度循环循环。 当调度多个循环循环时，该设备首先调度其循环头对循环中的另一循环没有依赖性的显性循环。