公开(公告)号：US09012967B2

公开(公告)日：2015-04-21

申请号：US13369894

申请日：2012-02-09

Applicant: Yi-Ching Lin ,  Chun-Yao Chen ,  Chen-Jong Wang ,  Shou-Gwo Wuu ,  Chung S. Wang ,  Chien-Hua Huang ,  Kun-Lung Chen ,  Ping Yang

Inventor： Yi-Ching Lin ,  Chun-Yao Chen ,  Chen-Jong Wang ,  Shou-Gwo Wuu ,  Chung S. Wang ,  Chien-Hua Huang ,  Kun-Lung Chen ,  Ping Yang

IPC: H01L27/108 ,  H01L29/94 ,  H01L27/02

CPC classification number: H01L27/10897 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10894

Abstract: Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.

Abstract translation: 嵌入式记忆 这些器件包括衬底，第一介电层，第二电介质层，第三电介质层和多个电容器。 衬底包括晶体管。 第一介电层，嵌入电连接其中的晶体管的第一和第二导电插塞覆盖在基板上。 包括暴露第一导电插塞的多个电容器开口的第二电介质层覆盖在第一电介质层上。 电容器包括分别设置在电容器开口中的多个底板，电连接第一导电插塞，分别覆盖在底板上的多个电容器电介质层，以及顶板，包括覆盖电容器电介质的顶板开口 层。 顶板开口暴露第二电介质层，并且顶板由电容器共享。

公开(公告)号：US20120139022A1

公开(公告)日：2012-06-07

申请号：US13369894

申请日：2012-02-09

Applicant: Yi-Ching Lin ,  Chun-Yao Chen ,  Chen-Jong Wang ,  Shou-Gwo Wuu ,  Chung S. Wang ,  Chien-Hua Huang ,  Kun-Lung Chen ,  Ping Yang

Inventor： Yi-Ching Lin ,  Chun-Yao Chen ,  Chen-Jong Wang ,  Shou-Gwo Wuu ,  Chung S. Wang ,  Chien-Hua Huang ,  Kun-Lung Chen ,  Ping Yang

IPC: H01L29/92 ,  H01L27/108

CPC classification number: H01L27/10897 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10894

Abstract: Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.

Abstract translation: 嵌入式记忆 这些器件包括衬底，第一介电层，第二电介质层，第三电介质层和多个电容器。 衬底包括晶体管。 第一介电层，嵌入电连接其中的晶体管的第一和第二导电插塞覆盖在基板上。 包括暴露第一导电插塞的多个电容器开口的第二电介质层覆盖在第一电介质层上。 电容器包括分别设置在电容器开口中的多个底板，电连接第一导电插塞，分别覆盖在底板上的多个电容器电介质层，以及顶板，包括覆盖电容器电介质的顶板开口 层。 顶板开口暴露第二电介质层，并且顶板由电容器共享。

公开(公告)号：US20110062663A1

公开(公告)日：2011-03-17

申请号：US12557782

申请日：2009-09-11

Applicant: YI-CHING LIN

Inventor： YI-CHING LIN

IPC: A63F3/00

CPC classification number: A63F3/00006 ,  A63F2003/00018

Abstract: A game apparatus includes (i) a game board having a major game track with several segments, a bad fate block randomly disposed in each segments and between adjacent pair segments, and a bright future block to set out along the major game track, each of the several segments including several sequential blocks respectively having indicia representing specific characters and an opportunity block, the game board further having a minor game track into which an individual player will be confined upon stepping onto the bad fate block and in which the confined player continues to proceed along the minor game track; (ii) a set of vision cards each for distribution to each individual player at the beginning of the game, each vision card designating an ultimate goal, required points and a set of treasured items for each player such that whoever obtaining the required points and the set of treasured items first will be declared a first winner of the game.

Abstract translation: 游戏装置包括：（i）游戏板，其具有多个段的主要游戏轨迹，随机地设置在每个段中和相邻的对段之间的坏命运块，以及沿主要游戏轨道设置的明亮的未来块， 所述多个段包括分别具有表示特定字符​​的标记的几个连续块和机会块，所述游戏板还具有小型游戏轨道，单个玩家将被限制在步进到所述坏命运块之后，并且所述限制玩家继续 沿着小游戏轨道继续进行; （ii）一组视觉卡片，每张视觉卡片分别在游戏开始时分发给每个玩家，每个视觉卡片为每个玩家指定最终目标，所需点数和一组珍贵物品，以便获得所需点数和 首先珍贵的物品将被宣布为游戏的第一名。

公开(公告)号：US20080227338A1

公开(公告)日：2008-09-18

申请号：US11829480

申请日：2007-07-27

Applicant: YI-CHING LIN ,  MING-CHOU KUO ,  JUNG-HUI HSU

Inventor： YI-CHING LIN ,  MING-CHOU KUO ,  JUNG-HUI HSU

IPC: H01R25/00

CPC classification number: H01R31/06 ,  H01R35/04

Abstract: A portable adapter includes a first body; a second body; a pivoting unit, mounted between the first body and the second body; a power input, mounted on the first body; a power output, mounted on the first body near to the pivoting unit; and at least one connector, mounted on the second body. The pivoting unit unfolds the first body and the second body in a manner such that the power output is partially hidden between the first body and the second body. The foldable structure of the portable adapter has a reduced volume and the power output is partially hidden during travel. When in use with a laptop, the first body and the second body unfold to an angle of 90 degrees relative to each other by means of the pivoting unit, so that the connector can be plugged with an electronic device.

Abstract translation: 便携式适配器包括第一主体; 第二个身体 枢转单元，安装在所述第一主体和所述第二主体之间; 电源输入，安装在第一机身上; 功率输出，安装在靠近枢转单元的第一主体上; 以及安装在第二主体上的至少一个连接器。 枢转单元以使得功率输出部分地隐藏在第一主体和第二主体之间的方式展开第一主体和第二主体。 便携式适配器的可折叠结构具有减小的体积，并且在行驶期间功率输出部分隐藏。 当与膝上型计算机一起使用时，第一主体和第二主体通过枢转单元相对于彼此展开成90度的角度，使得连接器可以用电子装置插入。

公开(公告)号：US20080090434A1

公开(公告)日：2008-04-17

申请号：US11637872

申请日：2006-12-13

Applicant: Yi-Ching Lin ,  Ming-Chou Kuo

Inventor： Yi-Ching Lin ,  Ming-Chou Kuo

IPC: H01R13/44

CPC classification number: H01R13/60 ,  H01R13/652 ,  H01R13/72 ,  H01R13/73 ,  H01R24/30 ,  H01R24/78 ,  H01R25/00 ,  H01R2103/00

Abstract: A retractable extension socket includes an socket body, a fixing structure, a receiving structure, a conducting wire and a plug. The fixing structure and the receiving structure are disposed on the socket body. One end of the conducting wire is connected to the socket body. The plug is connected to the other end of the conducting wire. Thus, a retractable extension socket is formed. The retractable extension socket can be used as an extension socket. In addition, by winding the cable into the socket body and attaching the plug into the fixing structure, the retractable extension socket can be used as a single plug. Furthermore, the plug can be collected into the receiving structure in order that it can be carried around easily.

Abstract translation: 可伸缩的延伸插座包括插座主体，固定结构，接收结构，导线和插头。 固定结构和接收结构设置在插座主体上。 导线的一端连接到插座主体。 插头连接到导线的另一端。 因此，形成了伸缩式伸缩插座。 伸缩式插座可用作扩展插座。 此外，通过将电缆卷绕到插座主体中并将插头连接到固定结构中，可伸缩的插座可用作单个插头。 此外，可以将插头收集到接收结构中，以便容易地携带。

公开(公告)号：US20060226174A1

公开(公告)日：2006-10-12

申请号：US11400315

申请日：2006-04-10

Applicant: Yi-Ching Lin

Inventor： Yi-Ching Lin

IPC: B65D88/54

CPC classification number: H04M1/0262 ,  H01M2/1066

Abstract: A mobile device with a releasable power storage device is provided. The mobile device comprises a cabinet, a power storage device detachably engaged with the cabinet, a latch disposed on the cabinet adjacent to a side wall thereof and capable of moving along the side, and an engaging portion engaged with the latch. The power storage device comprises a stopping portion and a guiding portion. The stopping portion and the engaging portion are alternatively disposed on one side of the body. When an external force is exerted on the engaging portion, the latch is moved to push the guiding portion of the power storage so as to eject the power storage device from the cabinet.

Abstract translation: 提供具有可释放的蓄电装置的移动装置。 移动装置包括机壳，与机壳可拆卸地接合的蓄电装置，与其侧壁相邻并能够沿着侧面移动的闩锁，以及与闩锁接合的接合部。 蓄电装置包括止动部和引导部。 止动部和接合部交替地设置在主体的一侧。 当外力作用在接合部分上时，闩锁被移动以推动电力存储器的引导部分，从而将电力存储装置从机柜中排出。

公开(公告)号：US06693359B1

公开(公告)日：2004-02-17

申请号：US10351328

申请日：2003-01-27

Applicant: Yi-Ching Lin

Inventor： Yi-Ching Lin

IPC: H01L2348

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/111 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/09436 ,  H05K2201/098 ,  Y02P70/611 ,  H01L2924/00015 ,  H01L2224/05599

Abstract: A semiconductor package, which is to attach an electric device, such as a die, thereon and electrically connect therewith, has a substrate with a conductor pattern thereon. The conductor pattern consists of a plurality of traces in a specific layout. The conductor pattern has conducting portions on which is provided with a conductor member respectively. The conductor members locate at positions above the conducting portion of the conductor pattern with a bottom surface thereof electrically connecting a top surface of the conducting portion. A solder mask is provided on the substrate sheltering the conductor pattern but exposing at least a top surface of the conductor member. Whereby, the conductor can electrically connect the electric device via the conductor members.

Abstract translation: 在其上附着诸如模具的电气装置并与其电连接的半导体封装件具有其上具有导体图案的基板。 导体图案由特定布局中的多个迹线组成。 导体图案具有分别设有导体部件的导电部分。 导体构件位于导体图案的导电部分上方的位置处，其底表面电连接导电部分的顶表面。 在衬底上设置阻焊导体图形，但暴露于导体构件的至少顶表面的焊接掩模。 由此，导体可以经由导体构件电连接电子装置。

公开(公告)号：US5171703A

公开(公告)日：1992-12-15

申请号：US749210

申请日：1991-08-23

Applicant: Yi-Ching Lin ,  Haiping Dun ,  Ragupathy V. Giridhar

Inventor： Yi-Ching Lin ,  Haiping Dun ,  Ragupathy V. Giridhar

IPC: H01L21/02 ,  H01L21/304 ,  H01L29/04

CPC classification number: H01L29/045 ,  Y10S148/115

Abstract: Methods of forming a semiconductor substrate and a device oriented substantially along a crystal direction other than a crystal direction that falls along a cleavage plane and the substrate and device formed by each method are disclosed. An ingot of monocrystalline material is formed and marked to denote a crystal direction other than a crystal direction that falls along a cleavage plane. The ingot is lapped to form a semiconductor substrate having a mark denoting a crystal direction other than a crystal direction that falls along a cleavage plane. A device is formed on the semiconductor substrate having a monocrystalline layer, such that a field oxide-active area edge or a gate electrode lies substantially along a crystal direction other than a crystal direction that falls along a cleavage plane. The present invention may be used on any device where dislocation defects, a lateral diffusion, or a lateral oxidation is to be minimized.

Abstract translation: 公开了形成半导体衬底的方法和基本上沿着沿着解理面落下的晶体方向以外的晶体方向取向的器件以及通过各种方法形成的衬底和器件。 形成单晶材料锭并将其标记为除了沿着解理面落下的晶体方向以外的晶体方向。 将锭重叠以形成具有表示沿着解理面落下的晶体方向以外的晶体方向的标记的半导体衬底。 在具有单晶层的半导体衬底上形成器件，使得场氧化物有源区边缘或栅电极基本上沿着沿着解理面落下的晶体方向以外的晶体方向。 本发明可以用于将位错缺陷，横向扩散或横向氧化最小化的任何装置。

公开(公告)号：US5139971A

公开(公告)日：1992-08-18

申请号：US712116

申请日：1991-06-07

Applicant: Ragupathy V. Giridhar ,  Philip E. Freiberger ,  Brian A. Kaiser ,  Yi-Ching Lin

Inventor： Ragupathy V. Giridhar ,  Philip E. Freiberger ,  Brian A. Kaiser ,  Yi-Ching Lin

IPC: H01L21/3105 ,  H01L21/768

CPC classification number: H01L21/76801 ,  H01L21/3105 ,  H01L21/76828 ,  Y10S438/902

Abstract: A method of forming a device having an intermetal dielectric film which is formed and annealed to prevent a significant quantity of ambient moisture from being absorbed by the intermetal dielectric film prior to passivation layer deposition is disclosed. An intermetal dielectric layer is formed over a substrate having a interconnection layer. A second interconnect layer is formed over the IMD layer. The substrate with the intermetal dielectric is annealed anytime between IMD formation and passivation layer deposition to produce a film that does not absorb a significant quantity of ambient moisture, and therefore, longer queue times can be utilized between the anneal and subsequent processing. The present invention reduces the amount of water in the device which reduces hot electron induced device degradation.

Abstract translation: 公开了一种形成具有形成和退火的金属间电介质膜的器件的方法，以防止在钝化层沉积之前由金属间介电膜吸收大量的环境水分。 在具有互连层的衬底上形成金属间电介质层。 在IMD层上形成第二互连层。 具有金属间电介质的衬底可以随时在IMD形成和钝化层沉积之间退火，以产生不吸收大量环境水分的膜，因此可以在退火和后续处理之间利用更长的排队时间。 本发明减少了装置中减少热电子诱发装置退化的水量。

公开(公告)号：US20080124875A1

公开(公告)日：2008-05-29

申请号：US11592204

申请日：2006-11-03

Applicant: Ken Liao ,  Kuo-Hua Pan ,  Yun-Hsiu Chen ,  Syun-Ming Jang ,  Yi-Ching Lin

Inventor： Ken Liao ,  Kuo-Hua Pan ,  Yun-Hsiu Chen ,  Syun-Ming Jang ,  Yi-Ching Lin

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/266 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636

Abstract: A method for forming a strained channel in a semiconductor device is provided, comprises providing of a transistor comprising a gate stack exposed with a gate electrode on a semiconductor substrate, a pair of source/drain regions in the substrate on opposite sides of the gate stack and a pair of spacers on opposing sidewalls of the gate stack. A passivation layer is formed to cover the gate electrode and spacers of the transistor. A passivation layer is formed to cover the gate electrode and the spacers. A recess region is formed in each of the source/drain regions, wherein an edge of the recess region aligns to an outer edge of the spacers. The recess regions are filled with a strain-exerting material, thereby forming a strained channel region in the semiconductor substrate between the source/drain regions.

Abstract translation: 提供了一种在半导体器件中形成应变通道的方法，包括提供晶体管，其包括在半导体衬底上暴露有栅极电极的栅极堆叠，在栅极堆叠的相对侧的衬底中的一对源极/漏极区域 以及在栅极堆叠的相对的侧壁上的一对隔板。 形成钝化层以覆盖晶体管的栅电极和间隔物。 形成钝化层以覆盖栅电极和间隔物。 在每个源极/漏极区域中形成凹陷区域，其中凹部区域的边缘与间隔物的外边缘对准。 用应变施加材料填充凹陷区域，从而在源极/漏极区域之间的半导体衬底中形成应变通道区域。