公开(公告)号：US20130234094A1

公开(公告)日：2013-09-12

申请号：US13416183

申请日：2012-03-09

Applicant: Ting-Chang Chang ,  Yong-En Syu ,  Fu-Yen Jian ,  Shih-Chieh Chang ,  Ying-Lang Wang

Inventor： Ting-Chang Chang ,  Yong-En Syu ,  Fu-Yen Jian ,  Shih-Chieh Chang ,  Ying-Lang Wang

IPC: H01L45/00

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/12 ,  H01L45/145 ,  H01L45/1608

Abstract: Methods and apparatuses for a resistive random access memory (RRAM) device are disclosed. The RRAM device comprises a bottom electrode, a resistive switching layer disposed on the bottom electrode, and a top electrode disposed on the resistive switching layer. The resistive switching layer is made of a composite of a metal, Si, and O. There may be an additional tunnel barrier layer between the top electrode and the bottom electrode. The top electrode and the bottom electrode may comprise multiple sub-layers.

Abstract translation: 公开了一种用于电阻随机存取存储器（RRAM）装置的方法和装置。 RRAM器件包括底电极，设置在底电极上的电阻开关层和设置在电阻开关层上的顶电极。 电阻开关层由金属，Si和O的复合材料制成。在顶部电极和底部电极之间可能存在额外的隧道势垒层。 顶部电极和底部电极可以包括多个子层。

公开(公告)号：US08427879B2

公开(公告)日：2013-04-23

申请号：US12644575

申请日：2009-12-22

Applicant: Ting-Chang Chang ,  Shih-Ching Chen ,  Te-Chih Chen ,  Fu-Yen Jian ,  Yong-En Syu

Inventor： Ting-Chang Chang ,  Shih-Ching Chen ,  Te-Chih Chen ,  Fu-Yen Jian ,  Yong-En Syu

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/0466 ,  G11C16/10 ,  H01L29/792

Abstract: There is a method for enabling a SONOS transistor to be used as both a switch and a memory. FN tunneling is carried out through the source or drain of the transistor, so as to further change the state of electrons stored in an upper charge storage layer adjacent to the drain or source, and the variation in gate-induced drain leakage is used to recognize the memory state of the drain and source. A stable threshold voltage of the transistor is always maintained during this operation. The present invention enables one single transistor having dual features of switch and memory, while being provided with a two-bit memory effect, thus providing a higher memory density in comparison with a general transistor.

Abstract translation: 存在使SONOS晶体管能够用作开关和存储器的方法。 通过晶体管的源极或漏极进行FN隧穿，从而进一步改变存储在与漏极或源极相邻的上部电荷存储层中的电子的状态，并且使用栅极引起的漏极泄漏的变化来识别 漏极和源的存储状态。 在此操作期间，始终保持晶体管的稳定阈值电压。 本发明使得具有开关和存储器的双重特征的单个晶体管同时具有两比特存储器效应，从而与通用晶体管相比提供了更高的存储器密度。

公开(公告)号：US09847478B2

公开(公告)日：2017-12-19

申请号：US13416183

申请日：2012-03-09

Applicant: Ting-Chang Chang ,  Yong-En Syu ,  Fu-Yen Jian ,  Shih-Chieh Chang ,  Ying-Lang Wang

Inventor： Ting-Chang Chang ,  Yong-En Syu ,  Fu-Yen Jian ,  Shih-Chieh Chang ,  Ying-Lang Wang

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/12 ,  H01L45/145 ,  H01L45/1608

Abstract: Methods and apparatuses for a resistive random access memory (RRAM) device are disclosed. The RRAM device comprises a bottom electrode, a resistive switching layer disposed on the bottom electrode, and a top electrode disposed on the resistive switching layer. The resistive switching layer is made of a composite of a metal, Si, and O. There may be an additional tunnel barrier layer between the top electrode and the bottom electrode. The top electrode and the bottom electrode may comprise multiple sub-layers.

公开(公告)号：US20130009124A1

公开(公告)日：2013-01-10

申请号：US13237368

申请日：2011-09-20

Applicant: Ting-Chang CHANG ,  Yong-En SYU ,  Fu-Yen JIAN ,  Ming-Jinn TSAI

Inventor： Ting-Chang CHANG ,  Yong-En SYU ,  Fu-Yen JIAN ,  Ming-Jinn TSAI

IPC: H01L45/00

CPC classification number: H01L45/08 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/146

Abstract: A type of resistance random access memory structure having the function of diode rectification includes a first electrode, a second electrode and a resistance conversion layer. The resistance conversion layer is disposed between the first electrode and the second electrode; and it includes a first oxidized insulating layer which is adjacently connected to the first electrode; a second oxidized insulating layer which is adjacently connected to the second electrode; as well as an energy barrier turning layer disposing between the first oxidized insulating layer and the second oxidized insulating layer. An energy barrier high can be adjusted and controlled to change the resistance by voltage between the energy barrier turning layer and the first oxidized insulating layer. A fixed energy barrier is formed between the second oxidized insulating layer and the energy barrier turning layer, so that the resistance random access memory element features the function of diode rectification.

Abstract translation: 具有二极管整流功能的电阻随机存取存储器结构的一种类型包括第一电极，第二电极和电阻转换层。 电阻转换层设置在第一电极和第二电极之间; 并且其包括相邻地连接到第一电极的第一氧化绝缘层; 第二氧化绝缘层，其相邻地连接到第二电极; 以及设置在第一氧化绝缘层和第二氧化绝缘层之间的能量阻挡层转移层。 可以调节和控制能量势垒高，以通过能量阻挡转移层和第一氧化绝缘层之间的电压来改变电阻。 在第二氧化绝缘层和能量阻挡层之间形成固定的能量势垒，使得电阻随机存取元件具有二极管整流功能。

公开(公告)号：US20110096610A1

公开(公告)日：2011-04-28

申请号：US12644575

申请日：2009-12-22

Applicant: Ting-Chang Chang ,  Shih-Ching Chen ,  Te-Chih Chen ,  Fu-Yen Jian ,  Yong-En Syu

Inventor： Ting-Chang Chang ,  Shih-Ching Chen ,  Te-Chih Chen ,  Fu-Yen Jian ,  Yong-En Syu

IPC: G11C16/04

CPC classification number: G11C16/0466 ,  G11C16/10 ,  H01L29/792

Abstract: There is a method for enabling a SONOS transistor to be used as both a switch and a memory. FN tunneling is carried out through the source or drain of the transistor, so as to further change the state of electrons stored in an upper charge storage layer adjacent to the drain or source, and the variation in gate-induced drain leakage is used to recognize the memory state of the drain and source. A stable threshold voltage of the transistor is always maintained during this operation. The present invention enables one single transistor having dual features of switch and memory, while being provided with a two-bit memory effect, thus providing a higher memory density in comparison with a general transistor.

Abstract translation: 存在使SONOS晶体管能够用作开关和存储器的方法。 通过晶体管的源极或漏极进行FN隧穿，从而进一步改变存储在与漏极或源极相邻的上部电荷存储层中的电子的状态，并且使用栅极引起的漏极泄漏的变化来识别 漏极和源的存储状态。 在此操作期间，始终保持晶体管的稳定阈值电压。 本发明使得具有开关和存储器的双重特征的单个晶体管同时具有两比特存储器效应，从而与通用晶体管相比提供了更高的存储器密度。