公开(公告)号：US10361082B2

公开(公告)日：2019-07-23

申请号：US15997298

申请日：2018-06-04

Applicant: ABB Schweiz AG

Inventor： Holger Bartolf ,  Munaf Rahimo ,  Lars Knoll ,  Andrei Mihaila ,  Renato Minamisawa

IPC: H01L21/266 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/10 ,  H01L29/16 ,  H01L21/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/20

Abstract: A method of manufacturing a semiconductor device is provided with: (a) providing a wide bandgap substrate product, (b) for forming two channel layers applying a first mask and applying a p first dopant, for forming two source regions forming a second mask by applying a further layer on the lateral sides of the first mask and applying an n second dopant, for forming two well layers forming a third mask by removing such part of the second mask between the source regions and applying a p third dopant, wherein a well layer depth is at least as large as a channel layer depth, (c) after step (b) for forming a plug applying a fourth mask, which covers the source regions and the channel layers and applying a p fourth dopant to a greater depth than the well layer depth and with a higher doping concentration than the well layers; wherein the well layers surround the plug in the lateral direction and separate it from the two source regions.

公开(公告)号：US10516022B2

公开(公告)日：2019-12-24

申请号：US15997307

申请日：2018-06-04

Applicant: ABB Schweiz AG

Inventor： Holger Bartolf ,  Munaf Rahimo ,  Lars Knoll ,  Andrei Mihaila ,  Renato Minamisawa

IPC: H01L21/00 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/16 ,  H01L29/739 ,  H01L21/02 ,  H01L21/04 ,  H01L21/265 ,  H01L21/266 ,  H01L21/302 ,  H01L21/308 ,  H01L29/08 ,  H01L29/20

Abstract: A wide bandgap semiconductor device is comprising an (n−) doped drift layer between a first main side and a second main side. On the first main side, n doped source regions are arranged which are laterally surrounded by p doped channel layers having a channel layer depth. P+ doped well layers having a well layer depth, which is at least as large as the channel layer depth is arranged at the bottom of the source regions. A p++ doped plug extends from a depth, which is at least as deep as the source layer depth and less deep than the well layer depth, to a plug depth, which is as least as deep as the well layer depth, and having a higher doping concentration than the well layers, is arranged between the source regions and well layers. On the first main side, an ohmic contact contacts as a first main electrode the source regions, the well layers and the plug.

公开(公告)号：US10553437B2

公开(公告)日：2020-02-04

申请号：US15996589

申请日：2018-06-04

Applicant: ABB Schweiz AG

Inventor： Holger Bartolf ,  Munaf Rahimo ,  Lars Knoll ,  Andrei Mihaila ,  Renato Minamisawa

IPC: H01L29/76 ,  H01L21/266 ,  H01L29/739 ,  H01L29/78 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66 ,  H01L21/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/20

Abstract: A method of manufacturing a semiconductor device is provided with: (a) providing a wide bandgap substrate product, (b) forming source regions by applying a first mask with a first and second mask layer and applying an n dopant, forming a well layer by removing such part of the first mask, which is arranged between the two source regions, and applying a p dopant, forming two channel regions by forming a third mask by performing an etching step, by which the first mask layer is farther removed at the openings than the second mask layer, and then removing the second mask layer, wherein the remaining first mask layer forms a third mask and applying a p dopant, wherein a well layer depth is at least as large as a channel layer depth, (c) after step (b) for forming a plug applying a fourth mask, which covers the source regions and the channel layers and applying a p fourth dopant to a greater depth than the well layer depth and with a higher doping concentration than the well layers.

公开(公告)号：US20190035928A1

公开(公告)日：2019-01-31

申请号：US16149220

申请日：2018-10-02

Applicant: ABB Schweiz AG

Inventor： Renato Minamisawa ,  Lars Knoll

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L29/06 ,  H01L29/36 ,  H01L29/16 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04

Abstract: The present application provides a power semiconductor device having a low on-state resistance while avoiding any short channel effects and having a low subthreshold slope. To attain this object the invention provides a trench power semiconductor device, which includes a compensation layer of a first conductivity type, wherein the compensation layer is extending on a gate insulation layer between a source layer of the first conductivity type and a substrate layer of the first conductivity type directly adjacent to a channel region of a second conductivity type, and wherein: L ch > 4  √ ( ɛ CR  t COMP  t GI ɛ GI ) . In the above inequation Lch is a channel length, εCR is a permittivity of the channel region, εGI is a permittivity of the gate insulation layer, tCOMP is a thickness of the compensation layer and tGI is a thickness of the gate insulation layer.

公开(公告)号：US10164126B2

公开(公告)日：2018-12-25

申请号：US15861230

申请日：2018-01-03

Applicant: ABB Schweiz AG

Inventor： Andrei Mihaila ,  Munaf Rahimo ,  Renato Minamisawa ,  Lars Knoll ,  Liutauras Storasta

IPC: H01L29/06 ,  H01L29/872 ,  H01L29/08 ,  H01L29/16 ,  H01L29/20

Abstract: A semiconductor power rectifier with increased surge current capability is described. A semiconductor layer includes a drift layer having a first conductivity type, at least one pilot region having a second conductivity type different from the first conductivity type, a plurality of stripe-shaped emitter regions having the second conductivity type, and a transition region having the second conductivity type, wherein the at least one pilot region has in any lateral direction parallel to the first main side a width of at least 200 μm and is formed adjacent to the first main side to form a first p-n junction with the drift layer, each emitter region is formed adjacent to the first main side form a second p-n junction with the drift layer, and the transition region is formed adjacent to the first main side to form a third p-n junction with the drift layer.

公开(公告)号：US20180350977A1

公开(公告)日：2018-12-06

申请号：US16052981

申请日：2018-08-02

Applicant: ABB Schweiz AG

Inventor： Lars Knoll ,  Renato Minamisawa

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/4238

Abstract: A power semiconductor device includes a plurality of vertical field effect transistor cells arranged in a plurality of parallel rows, each row including vertical field effect transistor cells arranged along a first direction, wherein in each vertical field effect transistor cell a body region is surrounded by the gate layer from two lateral surfaces of the body region opposite to each other. In each row of vertical field effect transistor cells the body regions are separated from each other in the first direction by first gate regions of the gate layer, each first gate region penetrating through the body layer, so that in each row of vertical field effect transistor cells the first gate regions alternate with the body regions along the first direction. The first gate regions within each row of vertical field effect transistor cells are connected with each other by second gate regions extending across the body regions of the respective vertical field effect transistor cells in the first direction. The first gate regions and the second gate regions form continuous gate strips extending with its longitudinal axis in the first direction. A source electrode is formed on the source layer to form a first ohmic contact to the source layer between each pair of adjacent gate strips. The whole top surface of the body region facing away from the substrate layer is in direct contact with the gate insulation layer.

公开(公告)号：US20180212071A1

公开(公告)日：2018-07-26

申请号：US15861230

申请日：2018-01-03

Applicant: ABB Schweiz AG

Inventor： Andrei Mihaila ,  Munaf Rahimo ,  Renato Minamisawa ,  Lars Knoll ,  Liutauras Storasta

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/872 ,  H01L29/0619 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0813 ,  H01L29/1608 ,  H01L29/2003

Abstract: A semiconductor power rectifier with increased surge current capability is described, which has a semiconductor layer having a first main side and a second main side opposite to the first main side. The semiconductor layer includes a drift layer having a first conductivity type, at least one pilot region having a second conductivity type different from the first conductivity type, a plurality of stripe-shaped emitter regions having the second conductivity type, and a transition region having the second conductivity type, wherein the at least one pilot region has in any lateral direction parallel to the first main side a width of at least 200 μm and is formed adjacent to the first main side to form a first p-n junction with the drift layer, each emitter region is formed adjacent to the first main side form a second p-n junction with the drift layer, and the transition region is formed adjacent to the first main side to form a third p-n junction with the drift layer. The at least one pilot region is connected to the transition region by the plurality of stripe-shaped emitter regions.

公开(公告)号：US20210043735A1

公开(公告)日：2021-02-11

申请号：US17079077

申请日：2020-10-23

Applicant: ABB SCHWEIZ AG

Inventor： Renato Minamisawa ,  Lars Knoll

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: An embodiment provides a power semiconductor device having a low on-state resistance while avoiding any short channel effects and having a low subthreshold slope. The embodiment provides a trench power semiconductor device, which comprises a compensation layer of a first conductivity type, wherein the compensation layer is extending on a gate insulation layer between a source layer of the first conductivity type and a substrate layer of the first conductivity type directly adjacent to a channel region of a second conductivity type.

公开(公告)号：US20200006496A1

公开(公告)日：2020-01-02

申请号：US16558935

申请日：2019-09-03

Applicant: ABB Schweiz AG

Inventor： Friedhelm Bauer ,  Lars Knoll ,  Marco Bellini ,  Renato Minamisawa ,  Umamaheswara Vemulapati

IPC: H01L29/16 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: A power semiconductor device includes a semiconductor wafer having a first main side surface and a second main side surface. The semiconductor wafer includes a first semiconductor layer having a first conductivity type and a plurality of columnar or plate-shaped first semiconductor regions extending in the first semiconductor layer between the first main side surface and the second main side surface in a vertical direction perpendicular to the first main side surface and the second main side surface. The first semiconductor regions have a second conductivity type, which is different from the first conductivity type. Therein, the first semiconductor is a layer of hexagonal silicon carbide. The first semiconductor regions are regions of 3C polytype silicon carbide.

公开(公告)号：US20180350943A1

公开(公告)日：2018-12-06

申请号：US15997307

申请日：2018-06-04

Applicant: ABB Schweiz AG

Inventor： Holger Bartolf ,  Munaf Rahimo ,  Lars Knoll ,  Andrei Mihaila ,  Renato Minamisawa

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L21/768 ,  H01L21/308

Abstract: A wide bandgap semiconductor device is comprising an (n−) doped drift layer between a first main side and a second main side. On the first main side, n doped source regions are arranged which are laterally surrounded by p doped channel layers having a channel layer depth. P+ doped well layers having a well layer depth, which is at least as large as the channel layer depth is arranged at the bottom of the source regions. A p++ doped plug extends from a depth, which is at least as deep as the source layer depth and less deep than the well layer depth, to a plug depth, which is as least as deep as the well layer depth, and having a higher doping concentration than the well layers, is arranged between the source regions and well layers. On the first main side, an ohmic contact contacts as a first main electrode the source regions, the well layers and the plug.