公开(公告)号：US20250149510A1

公开(公告)日：2025-05-08

申请号：US19013905

申请日：2025-01-08

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Paul M. Enquist ,  Gaius Gillman Fountain, JR.

IPC: H01L25/065 ,  H01L21/20 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H10D1/47 ,  H10D88/00

Abstract: A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.

公开(公告)号：US11631586B2

公开(公告)日：2023-04-18

申请号：US16914169

申请日：2020-06-26

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Paul M. Enquist ,  Gaius Gillman Fountain

IPC: H01L21/20 ,  H01L23/498 ,  H01L21/768 ,  H01L25/00 ,  H01L49/02 ,  H01L27/06 ,  H01L21/683 ,  H01L23/00 ,  H01L25/065

Abstract: A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.

公开(公告)号：US20240088120A1

公开(公告)日：2024-03-14

申请号：US18507478

申请日：2023-11-13

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Paul M. Enquist ,  Belgacem Haba

IPC: H01L25/00 ,  H01L21/768 ,  H01L21/822 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/07 ,  H01L25/18 ,  H01L27/146

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/09 ,  H01L25/074 ,  H01L25/18 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14687 ,  H01L27/1469 ,  H01L2224/02379 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

公开(公告)号：US12199069B2

公开(公告)日：2025-01-14

申请号：US18147180

申请日：2022-12-28

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Paul M. Enquist ,  Gaius Gillman Fountain, Jr.

IPC: H01L23/49 ,  H01L21/20 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L27/06 ,  H01L49/02

Abstract: A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.

公开(公告)号：US11916054B2

公开(公告)日：2024-02-27

申请号：US17586236

申请日：2022-01-27

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Paul M. Enquist ,  Belgacem Haba

IPC: H01L25/18 ,  H01L27/146 ,  H01L21/822 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L25/07 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/09 ,  H01L25/074 ,  H01L25/50 ,  H01L27/1469 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14687 ,  H01L2224/02379 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

公开(公告)号：US20240243085A1

公开(公告)日：2024-07-18

申请号：US18517681

申请日：2023-11-22

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Paul M. Enquist

IPC: H01L23/00 ,  H01L21/50 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/09 ,  H01L21/50 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/036 ,  H01L2224/03616 ,  H01L2224/03825 ,  H01L2224/05005 ,  H01L2224/05007 ,  H01L2224/05026 ,  H01L2224/05078 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/0556 ,  H01L2224/05561 ,  H01L2224/05562 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/08112 ,  H01L2224/08121 ,  H01L2224/08123 ,  H01L2224/08145 ,  H01L2224/08147 ,  H01L2224/80011 ,  H01L2224/80031 ,  H01L2224/80035 ,  H01L2224/80047 ,  H01L2224/80075 ,  H01L2224/80097 ,  H01L2224/80099 ,  H01L2224/8019 ,  H01L2224/80194 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80935 ,  H01L2224/80986 ,  H01L2225/06513

Abstract: A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

公开(公告)号：US11830838B2

公开(公告)日：2023-11-28

申请号：US17677161

申请日：2022-02-22

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Paul M. Enquist

IPC: H01L23/00 ,  H01L21/50 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/09 ,  H01L21/50 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/036 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/03825 ,  H01L2224/05005 ,  H01L2224/05007 ,  H01L2224/05026 ,  H01L2224/0556 ,  H01L2224/0557 ,  H01L2224/05078 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05562 ,  H01L2224/05573 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/08112 ,  H01L2224/08121 ,  H01L2224/08123 ,  H01L2224/08145 ,  H01L2224/08147 ,  H01L2224/80011 ,  H01L2224/8019 ,  H01L2224/80031 ,  H01L2224/80035 ,  H01L2224/80047 ,  H01L2224/80075 ,  H01L2224/80097 ,  H01L2224/80099 ,  H01L2224/80194 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80935 ,  H01L2224/80986 ,  H01L2225/06513 ,  H01L2224/03462 ,  H01L2924/00014 ,  H01L2224/0345 ,  H01L2924/00014 ,  H01L2224/03452 ,  H01L2924/00014 ,  H01L2224/29339 ,  H01L2924/00014 ,  H01L2224/29386 ,  H01L2224/80895 ,  H01L2924/053 ,  H01L2224/80986 ,  H01L2224/80896 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/00014 ,  H01L2224/05686 ,  H01L2924/04941 ,  H01L2224/05686 ,  H01L2924/04953 ,  H01L2224/05684 ,  H01L2924/049 ,  H01L2224/05676 ,  H01L2924/053 ,  H01L2224/05681 ,  H01L2924/01014 ,  H01L2924/049 ,  H01L2224/05666 ,  H01L2924/01014 ,  H01L2924/049 ,  H01L2224/05684 ,  H01L2924/01005 ,  H01L2924/049 ,  H01L2224/05655 ,  H01L2924/051 ,  H01L2924/00014 ,  H01L2224/05657 ,  H01L2924/01074 ,  H01L2224/05657 ,  H01L2924/01074 ,  H01L2924/042

Abstract: A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

公开(公告)号：US20230282634A1

公开(公告)日：2023-09-07

申请号：US18148351

申请日：2022-12-29

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Paul M. Enquist ,  Belgacem Haba

IPC: H01L25/00 ,  H01L25/18 ,  H01L27/146 ,  H01L21/822 ,  H01L23/31 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L25/07

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/09 ,  H01L25/074 ,  H01L25/18 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14687 ,  H01L27/1469 ,  H01L2224/02379 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

公开(公告)号：US20230207322A1

公开(公告)日：2023-06-29

申请号：US18147180

申请日：2022-12-28

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Paul M. Enquist ,  Gaius Gillman Fountain, JR.

IPC: H01L21/20 ,  H01L23/498 ,  H01L21/768 ,  H01L25/00 ,  H01L27/06 ,  H01L21/683 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L21/2007 ,  H01L23/49866 ,  H01L21/76898 ,  H01L25/50 ,  H01L28/26 ,  H01L27/0688 ,  H01L21/6835 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2221/68359 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/83053 ,  H01L2224/83201 ,  H01L2225/06541

Abstract: A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.

公开(公告)号：US11515202B2

公开(公告)日：2022-11-29

申请号：US17315166

申请日：2021-05-07

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Paul M. Enquist ,  Gaius Gillman Fountain, Jr. ,  Qin-Yi Tong

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L25/00 ,  H01L27/06

Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.