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    Retiming with fixed power-up states
    2.
    发明授权
    Retiming with fixed power-up states 有权

    公开(公告)号：US10296701B1

    公开(公告)日：2019-05-21

    申请号：US15195837

    申请日：2016-06-28

    Applicant: ALTERA CORPORATION

    Inventor： Mahesh A. Iyer ,  Vasudeva M. Kamath ,  Robert Lawrence Walker

    IPC: G06F17/50

    Abstract: A computer-implemented method includes performing retiming using a circuit design to determine a retimed variation to the circuit design. The circuit design includes a first set of registers with defined power-up states and the variations each comprise a second set of registers that correspond to the first set of registers. The method includes maintaining fixed power-up states for the second set of registers in the variations. The fixed power-up states for the second set of registers are equivalent to the defined power-up states of the first set of registers. The method includes identifying registers of the second set of registers involved in an initial state conflict, and performing a mitigating action to resolve the initial state conflict to enable retiming to continue while maintaining functionally equivalent behavior as the circuit design. Various choices of initial states are also explored during retiming to increase the effect of retiming.

    Methods for minimizing logic overlap on integrated circuits
    3.
    发明授权
    Methods for minimizing logic overlap on integrated circuits 有权

    公开(公告)号：US10242144B1

    公开(公告)日：2019-03-26

    申请号：US15338134

    申请日：2016-10-28

    Applicant: Altera Corporation

    Inventor： Saurabh Adya ,  Mahesh A. Iyer ,  Love Singhal

    IPC: G06F17/50

    Abstract: Configuration data for an integrated circuit may be generated using logic design equipment to implement an optimal design on the integrated circuit. Implementing the optimal design may include placing hardware resources within the integrated circuit to decrease or remove overlaps between corresponding hardware resources. A given hardware resource may be defined as a rectangular region, an adjacent hardware resource may be defined as another rectangular region, and together, they may be defined as a hardware resource pair. The hardware resource pair may define an overlap region, with which a cost function may be associated. The cost function may be minimized in conjunction with other types of cost functions using a solver. The solver may generate coordinates that minimize or remove overlap to be implemented in the optimal design.

    Partial reconfiguration debugging using hybrid models
    4.
    发明授权
    Partial reconfiguration debugging using hybrid models 有权

    公开(公告)号：US10235485B1

    公开(公告)日：2019-03-19

    申请号：US15277376

    申请日：2016-09-27

    Applicant: Altera Corporation

    Inventor： Mahesh A. Iyer ,  Kalen B. Brunham

    IPC: G06F17/50

    Abstract: Circuitry for the simulation of partial reconfiguration of a logic design for an integrated circuit device using a hybrid model is provided. The circuitry may create a hybrid model by combining structural model netlists of one or more partial reconfiguration partitions of the logic design with a behavioral model of a static partition of the logic design. The hybrid model may undergo partial reconfiguration verification to ensure that undefined signals do not bypass a freeze bridge and pass from registers in the partial reconfiguration partitions to the static partition, and to ensure that these registers are each in a defined state after the partial reconfiguration operation and a register reset operation are completed.

    Sector-based clock routing methods and apparatus
    5.
    发明授权
    Sector-based clock routing methods and apparatus 有权

    公开(公告)号：US09922157B1

    公开(公告)日：2018-03-20

    申请号：US14802702

    申请日：2015-07-17

    Applicant: Altera Corporation

    Inventor： Carl Ebeling ,  Herman Henry Schmit ,  Dana How ,  Mahesh A. Iyer ,  Saurabh Adya

    IPC: G06F17/50

    CPC classification number: G06F17/5077 ,  G06F17/5081

    Abstract: A clock-tree construction method for a configurable clock grid structure having a plurality of sectors and a plurality of wire segments includes defining a clock region within the clock grid structure and constructing an H-tree that has a smallest size to cover the clock region. The method further includes aligning the clock region within the H-tree, pruning the H-tree and removing an unused segment from the H-tree. The method further includes performing a tree height reduction procedure to the pruned H-tree, and generating a clock tree with a reduced size or a reduced height from the tree height reduction procedure.

    Method and apparatus for verifying initial state equivalence of changed registers in retimed circuits
    7.
    发明授权
    Method and apparatus for verifying initial state equivalence of changed registers in retimed circuits 有权

    公开(公告)号：US10706203B1

    公开(公告)日：2020-07-07

    申请号：US15079518

    申请日：2016-03-24

    Applicant: Altera Corporation

    Inventor： Mahesh A. Iyer

    IPC: G06F30/398 ,  G06F30/30

    Abstract: A method for designing a system on a target device includes performing register retiming on an original design to generate a retimed design of the system. Compare points are identified in the original design and the retimed design. Equality constraints are defined for all compare points. Starting from the initial states of the original and retimed circuits, bounded sequential logic simulation is performed for a maximum number of time frames determined as the maximum absolute value of retiming variables computed during structural verification. Whether changed flip-flops in the retimed design have initial states that are correct are determined by comparing signal values at the compare points from the bounded sequential logic simulation.

    Method and apparatus for performing register retiming by utilizing native timing-driven constraints
    9.
    发明授权
    Method and apparatus for performing register retiming by utilizing native timing-driven constraints 有权

    公开(公告)号：US10417374B1

    公开(公告)日：2019-09-17

    申请号：US15150124

    申请日：2016-05-09

    Applicant: Altera Corporation

    Inventor： Mahesh A. Iyer

    IPC: G06F17/50

    Abstract: A method for designing a system on a target device includes synthesizing the system. The system is placed on the target device. The system is routed on the target device. Register retiming is performed on the system by applying timing analysis constraints, retiming constraints, bound constraints, and ordering constraints when solving for retiming labels that represent a number and direction of register movement along a path between nodes in the system, and arrival times on all nodes in the system to reflect the maximum delay in the system, to improve timing and meet target delay constraints.

    Methods for incremental circuit design legalization during physical synthesis
    10.
    发明授权
    Methods for incremental circuit design legalization during physical synthesis 有权

    公开(公告)号：US10339241B1

    公开(公告)日：2019-07-02

    申请号：US15154785

    申请日：2016-05-13

    Applicant: Altera Corporation

    Inventor： Mahesh A. Iyer ,  Robert Walker

    IPC: G06F17/50 ,  G06F8/71

    Abstract: Configuration data for an integrated circuit may be generated using logic design equipment to implement a logic design on the integrated circuit. The equipment may perform incremental physical synthesis, timing optimization, and legalization operations on the logic design. The equipment may identify timing and legalization constraints and logic blocks that fail the timing constraints, and may determine whether modifying and/or moving the blocks to new locations satisfy the legalization constraints while improving the timing of the design. If the legalization constraints are not satisfied, the design equipment may recursively move non-critical logic blocks to new locations while ensuring that the legalization and timing constraints are satisfied for each move such that the timing of the design is improved. This may be repeated in multiple rounds of adjustment. A netlist may be generated after the moves are performed. The configuration data may be generated based on the netlist.

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