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    Data handoff between randomized clock domain to fixed clock domain
    1.
    发明授权
    Data handoff between randomized clock domain to fixed clock domain 有权

    公开(公告)号：US10057048B2

    公开(公告)日：2018-08-21

    申请号：US15214176

    申请日：2016-07-19

    Applicant: ANALOG DEVICES, INC.

    Inventor： Eric Otte

    IPC: H04L7/00 ,  H04L7/02

    CPC classification number: H04L7/02 ,  H03M1/0624 ,  H03M1/0673 ,  H03M1/1215

    Abstract: A time-interleaved analog-to-digital converter (ADC) having M ADCs can increase the sampling speed several times compared to the sampling speed of just one ADC. Some time-interleaved ADCs randomize the order of the M ADCs sampling the analog input signal to improve dynamic performance. Randomization causes the output data of the M ADCs to be valid at randomized time instants. When the output data is sampled using a rising edge of a fixed clock, the output data can be valid just before, valid right at, or only valid for a short period of time after, the rising edge. Therefore, the setup or hold time can be very short. To address this issue, information regarding the randomized selection of an ADC is used to control the sampling occurring in the fixed clock domain and avoid the short setup or hold time.

    Efficient calibration of errors in multi-stage analog-to-digital converter
    2.
    发明授权
    Efficient calibration of errors in multi-stage analog-to-digital converter 有权
    在多级模数转换器中有效校准误差

    公开(公告)号：US09503116B2

    公开(公告)日：2016-11-22

    申请号：US14955916

    申请日：2015-12-01

    Applicant: ANALOG DEVICES, INC.

    Inventor： Carroll C. Speir ,  Eric Otte ,  Jeffrey Paul Bray

    IPC: H03M1/10 ,  H03M1/12 ,  H03M3/00 ,  H03M1/46

    CPC classification number: H03M1/128 ,  H03M1/1019 ,  H03M1/1028 ,  H03M1/12 ,  H03M1/121 ,  H03M1/1215 ,  H03M1/46 ,  H03M1/462 ,  H03M1/468 ,  H03M3/382 ,  H03M3/498

    Abstract: Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.

    Abstract translation: 模数转换器（ADC）可能会产生可能影响其性能的错误。 为了提高性能，已经使用许多技术来补偿或纠正错误。 当ADC采用亚微米技术实现时，ADC可以轻松轻松配备一个片上微处理器，用于执行各种数字功能。 片上微处理器和任何合适的数字电路可以实现减少这些错误的功能，从而能够减少某些不必要的伪像，并为高度可配置的ADC提供灵活的平台。 片上微处理器对于随机时间交织ADC特别有用。 此外，随机采样ADC可以并行添加到主ADC用于校准目的。 此外，整个系统可以包括用于校正ADC中的错误的有效实现。

    Signal path linearization
    3.
    发明授权
    Signal path linearization 有权

    公开(公告)号：US10340934B1

    公开(公告)日：2019-07-02

    申请号：US15845796

    申请日：2017-12-18

    Applicant: Analog Devices, Inc.

    Inventor： Nevena Rakuljic ,  Carroll C. Speir ,  Eric Otte ,  Corey Petersen ,  Jeffrey P. Bray

    IPC: H03M1/10 ,  H03M1/12

    Abstract: To address non-linearity, an on-chip linearization scheme is implemented along with an analog-to-digital converter (ADC) to measure and correct/tune for non-linearities and/or other non-idealities of the signal path having the ADC. The on-chip linearization scheme involves generating one or more test signals using an on-chip digital-to-analog converter (DAC) and providing the one or more test signals as input to the signal path to be linearized, and estimating non-linearity based on the one or more test signals and the output of the ADC. Test signals can include single-tone signals, multi-tone signals, and wideband signals spread over a range of frequencies. A time-delayed interleaving clocking scheme can be used to achieve a higher data rate for coefficient estimation without having to increase the sample rate of the ADC.

    Randomly sampling reference ADC for calibration
    4.
    发明授权
    Randomly sampling reference ADC for calibration 有权
    随机采样参考ADC进行校准

    公开(公告)号：US09525428B2

    公开(公告)日：2016-12-20

    申请号：US14955905

    申请日：2015-12-01

    Applicant: ANALOG DEVICES, INC.

    Inventor： Siddharth Devarajan ,  Eric Otte ,  Nevena Rakuljic ,  Carroll C. Speir

    IPC: H03M1/12 ,  H03M1/10 ,  H03M1/46 ,  H03M3/00

    CPC classification number: H03M1/128 ,  H03M1/1019 ,  H03M1/1028 ,  H03M1/12 ,  H03M1/121 ,  H03M1/1215 ,  H03M1/46 ,  H03M1/462 ,  H03M1/468 ,  H03M3/382 ,  H03M3/498

    Abstract: Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.

    Abstract translation: 模数转换器（ADC）可能会产生可能影响其性能的错误。 为了提高性能，已经使用许多技术来补偿或纠正错误。 当ADC采用亚微米技术实现时，ADC可以轻松轻松配备一个片上微处理器，用于执行各种数字功能。 片上微处理器和任何合适的数字电路可以实现减少这些错误的功能，从而能够减少某些不必要的伪像，并为高度可配置的ADC提供灵活的平台。 片上微处理器对于随机时间交织ADC特别有用。 此外，随机采样ADC可以并行添加到主ADC用于校准目的。 此外，整个系统可以包括用于校正ADC中的错误的有效实现。

    Histogram-based qualification of data used in background or blind calibration of interleaving errors of time-interleaved ADCS
    5.
    发明授权
    Histogram-based qualification of data used in background or blind calibration of interleaving errors of time-interleaved ADCS 有权

    公开(公告)号：US10536155B1

    公开(公告)日：2020-01-14

    申请号：US16138886

    申请日：2018-09-21

    Applicant: Analog Devices, Inc.

    Inventor： Eric Otte

    IPC: H03M1/06 ,  H03M1/10 ,  G06F11/07

    Abstract: An ADC can include a plurality of time-interleaved ADCs to increase the overall sampling rate of the ADC. Such an ADC can have interleaving errors, since the time-interleaved ADCs in the ADC are not always perfectly matched. One way to calibrate for these mismatches is by observing the digital output signals of the time-interleaved ADCs in the background, or more broadly, without knowledge of the input signal to the ADC (often referred to as “blind” calibration). Due to the nature of these calibrations, the performance of the calibration would significantly degrade when the input signal has certain problematic input conditions, such as a certain coherent input frequency. To address this issue, the data being used for calibration of interleaving errors can go through a qualifying process to assess whether to update error estimates based on the data.

    Measuring and correcting non-idealities of a system
    6.
    发明授权
    Measuring and correcting non-idealities of a system 有权

    公开(公告)号：US09945901B1

    公开(公告)日：2018-04-17

    申请号：US15296251

    申请日：2016-10-18

    Applicant: ANALOG DEVICES, INC.

    Inventor： Eric Otte

    IPC: H03M1/06 ,  G01R31/28 ,  G01R31/3167 ,  G01R31/3177

    CPC classification number: G01R31/2851 ,  G01R31/3167 ,  G01R31/3177 ,  H03M1/10

    Abstract: Many systems implement calibration schemes to measure and correct for the non-idealities. Such systems can be complex, which makes them impractical to implement since the cost can potentially outweigh the benefits of the calibration scheme. To implement efficient and effective calibration, non-idealities or errors of a system are detected, in foreground or in background, in a piecewise fashion based on, e.g., correlations of an output signal with an uncorrelated random signal, where the correlation results are processed separately for different open intervals of an error signal. Second order and third order correction terms can be easily determined based on three open intervals. In various embodiments, the calibration scheme can detect and correct for linear errors, (linear and non-linear) memory/frequency dependent errors, static nonlinearity errors, Hammerstein-style non-linearity errors, and Wiener-style non-linearity errors (cross-terms).

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