公开(公告)号：US09385696B1

公开(公告)日：2016-07-05

申请号：US14497629

申请日：2014-09-26

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Arun Jangity

IPC: G06F1/04 ,  H03K3/017 ,  H03K5/05 ,  H03K3/037

CPC classification number: H03K5/05 ,  H03K3/037

Abstract: Various aspects provide for generating a clock signal for a hold latch. A latch pulse generator generates a pulse clock signal based on a first clock signal associated with a first flip-flop component and a second clock signal associated with a second flip-flop component. A hold latch component receives the pulse clock signal generated by the latch pulse generator and generates a data signal that is transmitted to the second flip-flop component.

Abstract translation: 各种方面提供用于产生用于保持锁存器的时钟信号。 锁存脉冲发生器基于与第一触发器组件相关联的第一时钟信号和与第二触发器组件相关联的第二时钟信号产生脉冲时钟信号。 保持锁存器组件接收由锁存脉冲发生器产生的脉冲时钟信号，并产生传输到第二触发器部件的数据信号。

公开(公告)号：US09761521B1

公开(公告)日：2017-09-12

申请号：US14519271

申请日：2014-10-21

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Arun Jangity ,  Srini Gbalakrishnan ,  Tai Chong

IPC: H01L21/48 ,  H01L21/52 ,  H01L23/50 ,  H01L23/00

CPC classification number: H01L23/50 ,  H01L23/5286 ,  H01L24/46 ,  H01L24/85

Abstract: Various embodiments provide for flexible and robust power grid connectivity in a server on a chip environment. The power grid has three parallel conductors, (e.g., wires) which represent two power polarities. The outside two wires can be of a first polarity (e.g. Vdd), while the middle wire is of a second polarity (e.g., Vss). The polarities of the wires can also be switched, as long as the two outside wires have the same polarity, while the inside wire has a different polarity. Power pins from modules adjacent to the set of three wires make connections to the nearest wire of the matching polarity. In this way, every power pin on the modules can be connected to the power grid without need for special alignment or custom power pins.