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公开(公告)号：US11605149B2
公开(公告)日：2023-03-14
申请号：US17708500
申请日：2022-03-30
Applicant: ATI Technologies ULC
Inventor： Stephen L. Morein , Laurent Lefebvre , Andrew E. Gruber , Andi Skende
Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
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公开(公告)号：US11023996B2
公开(公告)日：2021-06-01
申请号：US17005703
申请日：2020-08-28
Applicant: ATI Technologies ULC
Inventor： Stephen L. Morein , Laurent Lefebvre , Andrew E. Gruber , Andi Skende
Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
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公开(公告)号：US10796400B2
公开(公告)日：2020-10-06
申请号：US16601260
申请日：2019-10-14
Applicant: ATI Technologies ULC
Inventor： Stephen L. Morein , Laurent Lefebvre , Andrew E. Gruber , Andi Skende
Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
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公开(公告)号：US20150154731A1
公开(公告)日：2015-06-04
申请号：US14614967
申请日：2015-02-05
Applicant: ATI Technologies ULC
Inventor： Stephen L. Morein , Laurent Lefebvre , Andrew E. Gruber , Andi Skende
CPC classification number: G06T1/20 , G06T15/005 , G06T15/80
Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
Abstract translation: 在一个示例中的图形处理架构通过将顶点数据发送到通用寄存器块来执行顶点操作操作和像素操作操作，并且通过处理器对顶点数据执行顶点操作，除非通用寄存器块在其中没有足够的可用空间 存储传入的顶点数据; 并且继续基于在指令存储器中保持的指令由处理器执行或正在执行的像素计算操作，直到通用寄存器块中的足够的寄存器变得可用为止。
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Patent Agency Ranking
公开(公告)号：US20230186423A1
公开(公告)日：2023-06-15
申请号：US18106572
申请日：2023-02-07
Applicant: ATI Technologies ULC
Inventor： Stephen L. Morein , Laurent Lefebvre , Andrew E. Gruber , Andi Skende
CPC classification number: G06T1/20 , G06T15/80 , G06T15/005
Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
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公开(公告)号：US11328382B2
公开(公告)日：2022-05-10
申请号：US17230129
申请日：2021-04-14
Applicant: ATI Technologies ULC
Inventor： Stephen L. Morein , Laurent Lefebvre , Andrew E. Gruber , Andi Skende
Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
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公开(公告)号：US09582846B2
公开(公告)日：2017-02-28
申请号：US14614967
申请日：2015-02-05
Applicant: ATI Technologies ULC
Inventor： Stephen L. Morein , Laurent Lefebvre , Andrew E. Gruber , Andi Skende
CPC classification number: G06T1/20 , G06T15/005 , G06T15/80
Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
Abstract translation: 在一个示例中的图形处理架构通过将顶点数据发送到通用寄存器块来执行顶点操作操作和像素操作操作，并且通过处理器对顶点数据执行顶点操作，除非通用寄存器块在其中没有足够的可用空间 存储传入的顶点数据; 并且继续基于在指令存储器中保持的指令由处理器执行或正在执行的像素计算操作，直到通用寄存器块中的足够的寄存器变得可用为止。
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公开(公告)号：US20160307356A1
公开(公告)日：2016-10-20
申请号：US15193647
申请日：2016-06-27
Applicant: ATI Technologies ULC
Inventor： Stephen L. Morein , Laurent Lefebvre , Andrew E. Gruber , Andi Skende
CPC classification number: G06T1/20 , G06T15/005 , G06T15/80
Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
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公开(公告)号：US20140300613A1
公开(公告)日：2014-10-09
申请号：US14312014
申请日：2014-06-23
Applicant: ATI Technologies ULC
Inventor： Stephen L. Morein , Laurent Lefebvre , Andrew E. Gruber , Andi Skende
IPC: G06T1/20
CPC classification number: G06T1/20 , G06T15/005 , G06T15/80
Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
Abstract translation: 在一个示例中的图形处理架构通过将顶点数据发送到通用寄存器块来执行顶点操作操作和像素操作操作，并且通过处理器对顶点数据执行顶点操作，除非通用寄存器块在其中没有足够的可用空间 存储传入的顶点数据; 并且继续基于在指令存储器中保持的指令由处理器执行或正在执行的像素计算操作，直到通用寄存器块中的足够的寄存器变得可用为止。
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