公开(公告)号：US09147700B2

公开(公告)日：2015-09-29

申请号：US14598205

申请日：2015-01-15

Applicant: AU Optronics Corp.

Inventor： Yi-Chen Chung ,  Chia-Yu Chen ,  Hui-Ling Ku ,  Yu-Hung Chen ,  Chi-Wei Chou ,  Fan-Wei Chang ,  Hsueh-Hsing Lu ,  Hung-Che Ting

IPC: H01L21/00 ,  H01L27/12 ,  H01L21/28 ,  H01L21/311

CPC classification number: H01L27/1288 ,  H01L21/28008 ,  H01L21/31133 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L2227/323

Abstract: A manufacturing method of an array substrate includes following steps. A first photolithography process is performed to form a gate electrode on a substrate. A gate insulating layer is formed to cover the substrate and the gate electrode. A second photolithography process is performed to form a patterned semiconductor layer and a patterned etching stop layer. A semiconductor layer and an etching stop layer are successively formed on the gate insulating layer, and a second patterned photoresist is formed on the etching stop layer. The etching stop layer uncovered by the second patterned photoresist is removed. The semiconductor layer uncovered by the second patterned photoresist is removed for forming the patterned semiconductor on the gate insulating layer. A patterned etching stop layer is formed on the patterned semiconductor layer by etching the second patterned photoresist and the etching stop layer.

Abstract translation: 阵列基板的制造方法包括以下步骤。 执行第一光刻工艺以在衬底上形成栅电极。 形成栅极绝缘层以覆盖基板和栅电极。 执行第二光刻工艺以形成图案化的半导体层和图案化的蚀刻停止层。 在栅极绝缘层上依次形成半导体层和蚀刻停止层，在蚀刻停止层上形成第二图案化光致抗蚀剂。 除去未被第二图案化光致抗蚀剂覆盖的蚀刻停止层。 去除未被第二图案化光致抗蚀剂覆盖的半导体层，以在栅极绝缘层上形成图案化的半导体。 通过蚀刻第二图案化光致抗蚀剂和蚀刻停止层，在图案化的半导体层上形成图案化的蚀刻停止层。

公开(公告)号：US20150126006A1

公开(公告)日：2015-05-07

申请号：US14598205

申请日：2015-01-15

Applicant: AU Optronics Corp.

Inventor： Yi-Chen Chung ,  Chia-Yu Chen ,  Hui-Ling Ku ,  Yu-Hung Chen ,  Chi-Wei Chou ,  Fan-Wei Chang ,  Hsueh-Hsing Lu ,  Hung-Che Ting

IPC: H01L27/12 ,  H01L21/311 ,  H01L21/28

CPC classification number: H01L27/1288 ,  H01L21/28008 ,  H01L21/31133 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L2227/323

Abstract: A manufacturing method of an array substrate includes following steps. A first photolithography process is performed to form a gate electrode on a substrate. A gate insulating layer is formed to cover the substrate and the gate electrode. A second photolithography process is performed to form a patterned semiconductor layer and a patterned etching stop layer. A semiconductor layer and an etching stop layer are successively formed on the gate insulating layer, and a second patterned photoresist is formed on the etching stop layer. The etching stop layer uncovered by the second patterned photoresist is removed. The semiconductor layer uncovered by the second patterned photoresist is removed for forming the patterned semiconductor on the gate insulating layer. A patterned etching stop layer is formed on the patterned semiconductor layer by etching the second patterned photoresist and the etching stop layer.

Abstract translation: 阵列基板的制造方法包括以下步骤。 执行第一光刻工艺以在衬底上形成栅电极。 形成栅极绝缘层以覆盖基板和栅电极。 执行第二光刻工艺以形成图案化的半导体层和图案化的蚀刻停止层。 在栅极绝缘层上依次形成半导体层和蚀刻停止层，在蚀刻停止层上形成第二图案化光致抗蚀剂。 除去未被第二图案化光致抗蚀剂覆盖的蚀刻停止层。 去除未被第二图案化光致抗蚀剂覆盖的半导体层，以在栅极绝缘层上形成图案化的半导体。 通过蚀刻第二图案化光致抗蚀剂和蚀刻停止层，在图案化的半导体层上形成图案化的蚀刻停止层。

公开(公告)号：US08674365B2

公开(公告)日：2014-03-18

申请号：US13668332

申请日：2012-11-05

Applicant: AU Optronics Corp.

Inventor： Hui-Ling Ku ,  Chia-Yu Chen ,  Yi-Chen Chung ,  Yu-Hung Chen ,  Chi-Wei Chou ,  Fan-Wei Chang ,  Hsueh-Hsing Lu ,  Hung-Che Ting

IPC: H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC classification number: H01L27/127 ,  H01L21/76 ,  H01L27/1225 ,  H01L27/1262 ,  H01L27/1288 ,  H01L29/6675

Abstract: A manufacturing method of an array substrate includes the following steps. A first conductive layer, a gate insulating layer, a semiconductor layer, an etching stop layer, and a first patterned photoresist are successively formed on a substrate. The etching stop layer and the semiconductor layer uncovered by the first patterned photoresist are then removed by a first etching process. A patterned gate insulating layer and a patterned etching stop layer are then formed through a second etching process. The first conductive layer uncovered by the patterned gate insulating layer is then removed to form a gate electrode. The semiconductor layer uncovered by the patterned etching stop layer is then removed to form a patterned semiconductor layer and partially expose the patterned gate insulating layer.

Abstract translation: 阵列基板的制造方法包括以下步骤。 在衬底上依次形成第一导电层，栅绝缘层，半导体层，蚀刻停止层和第一图案化光刻胶。 然后通过第一蚀刻工艺去除由第一图案化光致抗蚀剂未覆盖的蚀刻停止层和半导体层。 然后通过第二蚀刻工艺形成图案化的栅极绝缘层和图案化的蚀刻停止层。 然后去除由图案化的栅极绝缘层未覆盖的第一导电层以形成栅电极。 然后去除由图案化的蚀刻停止层未覆盖的半导体层以形成图案化的半导体层并且部分地暴露图案化的栅极绝缘层。

公开(公告)号：US20140127844A1

公开(公告)日：2014-05-08

申请号：US14155380

申请日：2014-01-15

Applicant: AU Optronics Corp.

Inventor： Hui-Ling Ku ,  Chia-Yu Chen ,  Yi-Chen Chung ,  Yu-Hung Chen ,  Chi-Wei Chou ,  Fan-Wei Chang ,  Hsueh-Hsing Lu ,  Hung-Che Ting

IPC: H01L27/12

CPC classification number: H01L27/127 ,  H01L21/76 ,  H01L27/1225 ,  H01L27/1262 ,  H01L27/1288 ,  H01L29/6675

Abstract: A manufacturing method of an array substrate includes the following steps. A first conductive layer, a gate insulating layer, a semiconductor layer, an etching stop layer, and a first patterned photoresist are successively formed on a substrate. The etching stop layer and the semiconductor layer uncovered by the first patterned photoresist are then removed by a first etching process. A patterned gate insulating layer and a patterned etching stop layer are then formed through a second etching process. The first conductive layer uncovered by the patterned gate insulating layer is then removed to form a gate electrode. The semiconductor layer uncovered by the patterned etching stop layer is then removed to form a patterned semiconductor layer and partially expose the patterned gate insulating layer.

Abstract translation: 阵列基板的制造方法包括以下步骤。 在衬底上依次形成第一导电层，栅绝缘层，半导体层，蚀刻停止层和第一图案化光刻胶。 然后通过第一蚀刻工艺去除由第一图案化的光刻胶未覆盖的蚀刻停止层和半导体层。 然后通过第二蚀刻工艺形成图案化的栅极绝缘层和图案化的蚀刻停止层。 然后去除由图案化的栅极绝缘层未覆盖的第一导电层以形成栅电极。 然后去除由图案化的蚀刻停止层未覆盖的半导体层以形成图案化的半导体层并且部分地暴露图案化的栅极绝缘层。

公开(公告)号：US20150123128A1

公开(公告)日：2015-05-07

申请号：US14598244

申请日：2015-01-16

Applicant: AU Optronics Corp.

Inventor： Yi-Chen Chung ,  Chia-Yu Chen ,  Hui-Ling Ku ,  Yu-Hung Chen ,  Chi-Wei Chou ,  Fan-Wei Chang ,  Hsueh-Hsing Lu ,  Hung-Che Ting

IPC: H01L27/12

CPC classification number: H01L27/1288 ,  H01L21/28008 ,  H01L21/31133 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L2227/323

Abstract: The array substrate includes a substrate, a thin film transistor (TFT) and a pixel electrode. The TFT is disposed on the substrate and includes a gate electrode, a gate insulating layer, a patterned semiconductor layer, a patterned etching stop layer, a patterned hard mask layer, a source electrode and a drain electrode. The patterned gate insulating layer is disposed on the gate electrode. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The patterned etching stop layer is disposed on the patterned semiconductor layer. The source and the drain electrodes are disposed on the patterned etching stop layer and the patterned semiconductor layer. The patterned hard mask layer is disposed between the source electrode and the patterned etching stop layer and disposed between the drain electrode and the patterned etching stop layer. The pixel electrode is disposed on the substrate and electrically connected to the TFT.

Abstract translation: 阵列基板包括基板，薄膜晶体管（TFT）和像素电极。 TFT设置在基板上，包括栅电极，栅极绝缘层，图案化半导体层，图案化蚀刻停止层，图案化硬掩模层，源电极和漏电极。 图案化的栅极绝缘层设置在栅电极上。 图案化的半导体层设置在图案化的栅极绝缘层上。 图案化的蚀刻停止层设置在图案化的半导体层上。 源极和漏极设置在图案化的刻蚀停止层和图案化的半导体层上。 图案化的硬掩模层设置在源电极和图案化的蚀刻停止层之间，并且设置在漏电极和图案化的蚀刻停止层之间。 像素电极设置在基板上并与TFT电连接。

公开(公告)号：US09263481B2

公开(公告)日：2016-02-16

申请号：US14598244

申请日：2015-01-16

Applicant: AU Optronics Corp.

Inventor： Yi-Chen Chung ,  Chia-Yu Chen ,  Hui-Ling Ku ,  Yu-Hung Chen ,  Chi-Wei Chou ,  Fan-Wei Chang ,  Hsueh-Hsing Lu ,  Hung-Che Ting

IPC: H01L27/14 ,  H01L27/12 ,  H01L21/28 ,  H01L21/311

CPC classification number: H01L27/1288 ,  H01L21/28008 ,  H01L21/31133 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L2227/323

Abstract: The array substrate includes a substrate, a thin film transistor (TFT) and a pixel electrode. The TFT is disposed on the substrate and includes a gate electrode, a gate insulating layer, a patterned semiconductor layer, a patterned etching stop layer, a patterned hard mask layer, a source electrode and a drain electrode. The patterned gate insulating layer is disposed on the gate electrode. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The patterned etching stop layer is disposed on the patterned semiconductor layer. The source and the drain electrodes are disposed on the patterned etching stop layer and the patterned semiconductor layer. The patterned hard mask layer is disposed between the source electrode and the patterned etching stop layer and disposed between the drain electrode and the patterned etching stop layer. The pixel electrode is disposed on the substrate and electrically connected to the TFT.

Abstract translation: 阵列基板包括基板，薄膜晶体管（TFT）和像素电极。 TFT设置在基板上，包括栅电极，栅极绝缘层，图案化半导体层，图案化蚀刻停止层，图案化硬掩模层，源电极和漏电极。 图案化的栅极绝缘层设置在栅电极上。 图案化的半导体层设置在图案化的栅极绝缘层上。 图案化的蚀刻停止层设置在图案化的半导体层上。 源极和漏极设置在图案化的刻蚀停止层和图案化的半导体层上。 图案化的硬掩模层设置在源电极和图案化的蚀刻停止层之间，并且设置在漏电极和图案化的蚀刻停止层之间。 像素电极设置在基板上并与TFT电连接。

公开(公告)号：US08759165B2

公开(公告)日：2014-06-24

申请号：US14155380

申请日：2014-01-15

Applicant: AU Optronics Corp.

Inventor： Hui-Ling Ku ,  Chia-Yu Chen ,  Yi-Chen Chung ,  Yu-Hung Chen ,  Chi-Wei Chou ,  Fan-Wei Chang ,  Hsueh-Hsing Lu ,  Hung-Che Ting

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L27/127 ,  H01L21/76 ,  H01L27/1225 ,  H01L27/1262 ,  H01L27/1288 ,  H01L29/6675

Abstract: A manufacturing method of an array substrate includes the following steps. A first conductive layer, a gate insulating layer, a semiconductor layer, an etching stop layer, and a first patterned photoresist are successively formed on a substrate. The etching stop layer and the semiconductor layer uncovered by the first patterned photoresist are then removed by a first etching process. A patterned gate insulating layer and a patterned etching stop layer are then formed through a second etching process. The first conductive layer uncovered by the patterned gate insulating layer is then removed to form a gate electrode. The semiconductor layer uncovered by the patterned etching stop layer is then removed to form a patterned semiconductor layer and partially expose the patterned gate insulating layer.

Abstract translation: 阵列基板的制造方法包括以下步骤。 在衬底上依次形成第一导电层，栅绝缘层，半导体层，蚀刻停止层和第一图案化光刻胶。 然后通过第一蚀刻工艺去除由第一图案化光致抗蚀剂未覆盖的蚀刻停止层和半导体层。 然后通过第二蚀刻工艺形成图案化的栅极绝缘层和图案化的蚀刻停止层。 然后去除由图案化的栅极绝缘层未覆盖的第一导电层以形成栅电极。 然后去除由图案化的蚀刻停止层未覆盖的半导体层以形成图案化的半导体层并且部分地暴露图案化的栅极绝缘层。

公开(公告)号：US20130161625A1

公开(公告)日：2013-06-27

申请号：US13668332

申请日：2012-11-05

Applicant: AU Optronics Corp.

Inventor： Hui-Ling Ku ,  Chia-Yu Chen ,  Yi-Chen Chung ,  Yu-Hung Chen ,  Chi-Wei Chou ,  Fan-Wei Chang ,  Hsueh-Hsing Lu ,  Hung-Che Ting

IPC: H01L29/66 ,  H01L21/76

CPC classification number: H01L27/127 ,  H01L21/76 ,  H01L27/1225 ,  H01L27/1262 ,  H01L27/1288 ,  H01L29/6675

Abstract: A manufacturing method of an array substrate includes the following steps. A first conductive layer, a gate insulating layer, a semiconductor layer, an etching stop layer, and a first patterned photoresist are successively formed on a substrate. The etching stop layer and the semiconductor layer uncovered by the first patterned photoresist are then removed by a first etching process. A patterned gate insulating layer and a patterned etching stop layer are then formed through a second etching process. The first conductive layer uncovered by the patterned gate insulating layer is then removed to form a gate electrode. The semiconductor layer uncovered by the patterned etching stop layer is then removed to form a patterned semiconductor layer and partially expose the patterned gate insulating layer.

Abstract translation: 阵列基板的制造方法包括以下步骤。 在衬底上依次形成第一导电层，栅绝缘层，半导体层，蚀刻停止层和第一图案化光刻胶。 然后通过第一蚀刻工艺去除由第一图案化光致抗蚀剂未覆盖的蚀刻停止层和半导体层。 然后通过第二蚀刻工艺形成图案化的栅极绝缘层和图案化的蚀刻停止层。 然后去除由图案化的栅极绝缘层未覆盖的第一导电层以形成栅电极。 然后去除由图案化的蚀刻停止层未覆盖的半导体层以形成图案化的半导体层并且部分地暴露图案化的栅极绝缘层。