公开(公告)号：US09171751B2

公开(公告)日：2015-10-27

申请号：US14264998

申请日：2014-04-29

Applicant: AVOGY, INC.

Inventor： Donald R. Disney ,  Andrew P. Edwards ,  Hui Nie ,  Richard J. Brown ,  Isik C. Kizilyalli ,  David P. Bour ,  Linda Romano ,  Thomas R. Prunty

IPC: H01L29/06 ,  H01L21/761 ,  H01L21/266 ,  H01L21/265 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/808 ,  H01L29/872

CPC classification number: H01L21/761 ,  H01L21/2654 ,  H01L21/266 ,  H01L21/765 ,  H01L29/0619 ,  H01L29/0642 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66136 ,  H01L29/66212 ,  H01L29/6631 ,  H01L29/66909 ,  H01L29/8083 ,  H01L29/872

Abstract: A method for fabricating an edge termination structure includes providing a substrate having a first surface and a second surface and a first conductivity type, forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate, and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The method also includes implanting ions into a first region of the second GaN epitaxial layer to electrically isolate a second region of the second GaN epitaxial layer from a third region of the second GaN epitaxial layer. The method further includes forming an active device coupled to the second region of the second GaN epitaxial layer and forming the edge termination structure coupled to the third region of the second GaN epitaxial layer.

Abstract translation: 一种用于制造边缘终端结构的方法包括提供具有第一表面和第二表面和第一导电类型的衬底，形成耦合到衬底的第一表面的第一导电类型的第一GaN外延层，并形成第二 与第一导电类型相反的第二导电类型的GaN外延层。 第二GaN外延层耦合到第一GaN外延层。 该方法还包括将离子注入第二GaN外延层的第一区域以将第二GaN外延层的第二区域与第二GaN外延层的第三区域电隔离。 该方法还包括形成耦合到第二GaN外延层的第二区域并形成耦合到第二GaN外延层的第三区域的边缘端接结构的有源器件。

公开(公告)号：US20140203328A1

公开(公告)日：2014-07-24

申请号：US14225334

申请日：2014-03-25

Applicant: Avogy, Inc.

Inventor： Donald R. Disney ,  Richard J. Brown ,  Hui Nie

IPC: H01L29/808

CPC classification number: H01L29/8083 ,  H01L29/2003 ,  H01L29/66909

Abstract: A semiconductor device includes a III-nitride substrate and a first III-nitride epitaxial layer coupled to the III-nitride substrate and comprising a drift region, a channel region, and an extension region. The channel region is separated from the III-nitride substrate by the drift region. The channel region is characterized by a first width. The extension region is separated from the drift region by the channel region. The extension region is characterized by a second width less than the first width. The semiconductor device also includes a second III-nitride epitaxial layer coupled to a top surface of the extension region, a III-nitride gate structure coupled to a sidewall of the channel region and laterally self-aligned with respect to the extension region, and a gate metal structure in electrical contact with the III-nitride gate structure and laterally self-aligned with respect to the extension region.

Abstract translation: 半导体器件包括III族氮化物衬底和耦合到III族氮化物衬底并且包括漂移区，沟道区和延伸区的第一III族氮化物外延层。 沟道区域通过漂移区域与III族氮化物衬底分离。 通道区域的特征在于第一宽度。 延伸区域通过沟道区域与漂移区域分离。 延伸区域的特征在于小于第一宽度的第二宽度。 半导体器件还包括耦合到延伸区域的顶表面的第二III族氮化物外延层，耦合到沟道区域的侧壁并相对于延伸区域横向自对准的III族氮化物栅极结构，以及 栅极金属结构与III族氮化物栅极结构电接触并且相对于延伸区域横向自对准。

公开(公告)号：US20140183543A1

公开(公告)日：2014-07-03

申请号：US13730619

申请日：2012-12-28

Applicant: AVOGY, INC.

Inventor： Donald R. Disney ,  Hemal N. Shah

IPC: H01L27/06 ,  H01L23/00

CPC classification number: H01L21/50 ,  H01L21/8252 ,  H01L23/49513 ,  H01L23/49517 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/2003 ,  H01L29/872 ,  H01L2021/6027 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05556 ,  H01L2224/0603 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2224/8384 ,  H01L2224/83855 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1033 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/0665

Abstract: An electronic package includes a leadframe, a plurality of pins, a gallium-nitride (GaN) transistor, and a GaN diode. The GaN transistor includes a drain region, a drift region, a source region, and a gate region; the drain region includes a GaN substrate and a drain contact, the drift region includes a first GaN epitaxial layer coupled to the GaN substrate, the source region includes a source contact and is separated from the GaN substrate by the drift region, and the gate region includes a second GaN epitaxial layer and a gate contact. The GaN diode includes an anode region and a cathode region, the cathode region including the GaN substrate and a cathode contact, and the anode region including a third GaN epitaxial layer coupled to the GaN substrate and an anode contact. The drain contact and the anode contact are electrically connected to the leadframe.

Abstract translation: 电子封装包括引线框，多个引脚，氮化镓（GaN）晶体管和GaN二极管。 GaN晶体管包括漏极区，漂移区，源极区和栅极区; 所述漏极区包括GaN衬底和漏极接触，所述漂移区包括耦合到所述GaN衬底的第一GaN外延层，所述源极区包括源极接触并且通过所述漂移区与所述GaN衬底分离，并且所述栅极区 包括第二GaN外延层和栅极接触。 GaN二极管包括阳极区域和阴极区域，阴极区域包括GaN衬底和阴极接触，并且阳极区域包括耦合到GaN衬底的第三GaN外延层和阳极接触。 漏极触点和阳极触点电连接到引线框架。

公开(公告)号：US09171900B2

公开(公告)日：2015-10-27

申请号：US14454524

申请日：2014-08-07

Applicant: Avogy, Inc.

Inventor： Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Richard J. Brown ,  Donald R. Disney

IPC: H01L29/868 ,  H01L29/20 ,  H01L21/20 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/868 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/66204 ,  H01L29/66212 ,  H01L29/6631 ,  H01L29/66924

Abstract: A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material. The implanted region of the first III-nitride epitaxial material has a reduced electrical conductivity in relation to portions of the first III-nitride epitaxial material adjacent to the implanted region.

Abstract translation: III族氮化物半导体器件包括用于在III族氮化物半导体器件的正向偏置操作期间支持电流的有源区域。 有源区包括具有第一导电类型的第一III族氮化物外延材料和具有第二导电类型的第二III族氮化物外延材料。 III族氮化物半导体器件还包括物理地邻近有源区的边缘终端区，并且包括包含第一III族氮化物外延材料的一部分的注入区。 第一III族氮化物外延材料的注入区域相对于与注入区域相邻的第一III族氮化物外延材料的部分具有降低的导电性。

公开(公告)号：US08937317B2

公开(公告)日：2015-01-20

申请号：US13730619

申请日：2012-12-28

Applicant: Avogy, Inc.

Inventor： Donald R. Disney ,  Hemal N. Shah

IPC: H01L31/0256 ,  H01L27/06 ,  H01L23/00 ,  H01L29/872

CPC classification number: H01L21/50 ,  H01L21/8252 ,  H01L23/49513 ,  H01L23/49517 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/2003 ,  H01L29/872 ,  H01L2021/6027 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05556 ,  H01L2224/0603 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2224/8384 ,  H01L2224/83855 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1033 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/0665

Abstract: An electronic package includes a leadframe, a plurality of pins, a gallium-nitride (GaN) transistor, and a GaN diode. The GaN transistor includes a drain region, a drift region, a source region, and a gate region; the drain region includes a GaN substrate and a drain contact, the drift region includes a first GaN epitaxial layer coupled to the GaN substrate, the source region includes a source contact and is separated from the GaN substrate by the drift region, and the gate region includes a second GaN epitaxial layer and a gate contact. The GaN diode includes an anode region and a cathode region, the cathode region including the GaN substrate and a cathode contact, and the anode region including a third GaN epitaxial layer coupled to the GaN substrate and an anode contact. The drain contact and the anode contact are electrically connected to the leadframe.

Abstract translation: 电子封装包括引线框，多个引脚，氮化镓（GaN）晶体管和GaN二极管。 GaN晶体管包括漏极区，漂移区，源极区和栅极区; 所述漏极区包括GaN衬底和漏极接触，所述漂移区包括耦合到所述GaN衬底的第一GaN外延层，所述源极区包括源极接触并且通过所述漂移区与所述GaN衬底分离，并且所述栅极区 包括第二GaN外延层和栅极接触。 GaN二极管包括阳极区域和阴极区域，阴极区域包括GaN衬底和阴极接触，并且阳极区域包括耦合到GaN衬底的第三GaN外延层和阳极接触。 漏极触点和阳极触点电连接到引线框架。

公开(公告)号：US20140346527A1

公开(公告)日：2014-11-27

申请号：US14454524

申请日：2014-08-07

Applicant: Avogy, Inc.

Inventor： Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Richard J. Brown ,  Donald R. Disney

IPC: H01L29/06 ,  H01L29/20 ,  H01L29/868

CPC classification number: H01L29/868 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/66204 ,  H01L29/66212 ,  H01L29/6631 ,  H01L29/66924

Abstract: A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material. The implanted region of the first III-nitride epitaxial material has a reduced electrical conductivity in relation to portions of the first III-nitride epitaxial material adjacent to the implanted region

Abstract translation: III族氮化物半导体器件包括用于在III族氮化物半导体器件的正向偏置操作期间支持电流的有源区域。 有源区包括具有第一导电类型的第一III族氮化物外延材料和具有第二导电类型的第二III族氮化物外延材料。 III族氮化物半导体器件还包括物理地邻近有源区的边缘终端区，并且包括包含第一III族氮化物外延材料的一部分的注入区。 第一III族氮化物外延材料的注入区域相对于邻近于注入区域的第一III族氮化物外延材料的部分具有降低的导电性

公开(公告)号：US20160013045A1

公开(公告)日：2016-01-14

申请号：US14617854

申请日：2015-02-09

Applicant: Avogy, Inc.

Inventor： Hui Nie ,  Donald R. Disney ,  Isik C. Kizilyalli

IPC: H01L21/02 ,  H01L21/683

CPC classification number: H01L21/0254 ,  H01L21/02645 ,  H01L21/6835 ,  H01L24/83 ,  H01L29/2003 ,  H01L29/66204 ,  H01L29/66212 ,  H01L29/66356 ,  H01L29/66446 ,  H01L29/739 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872 ,  H01L2221/68327 ,  H01L2224/04026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/32245 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2924/12032 ,  H01L2924/13062 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for fabricating an electronic device includes providing an engineered substrate structure comprising a III-nitride seed layer, forming GaN-based functional layers coupled to the III-nitride seed layer, and forming a first electrode structure electrically coupled to at least a portion of the GaN-based functional layers. The method also includes joining a carrier substrate opposing the GaN-based functional layers and removing at least a portion of the engineered substrate structure. The method further includes forming a second electrode structure electrically coupled to at least another portion of the GaN-based functional layers and removing the carrier substrate.

Abstract translation: 一种制造电子器件的方法包括提供包括III族氮化物种子层的工程化衬底结构，形成与III族氮化物种子层耦合的GaN基功能层，以及形成电耦合到至少一部分 GaN基功能层。 该方法还包括将与GaN基功能层相对的载体衬底接合并去除工程衬底结构的至少一部分。 该方法还包括形成电耦合到GaN基功能层的至少另一部分并去除载体衬底的第二电极结构。

公开(公告)号：US20150188521A1

公开(公告)日：2015-07-02

申请号：US14579202

申请日：2014-12-22

Applicant: Avogy, Inc.

Inventor： Hemal N. Shah ,  Donald R. Disney ,  Heratch Amirkhani Namagerdi

IPC: H03K3/012 ,  H01L29/739 ,  H01L29/20 ,  H01L29/80

CPC classification number: H03K3/012 ,  H01L29/2003 ,  H01L29/7393 ,  H01L29/80 ,  H03K17/04206 ,  H03K17/687

Abstract: An electronic circuit comprising a driver and a main transistor are provided. The driver may include a bias voltage generator, a supplementary transistor, and an output driver. The bias voltage generator may be configured to receive a voltage input and generate a biased voltage output based on the voltage input. The supplementary transistor may have a gate coupled to the biased voltage output of the bias voltage generator, and a source of the supplementary transistor providing a current to the bias voltage generator. The output driver may be configured to receive the biased voltage output from the bias voltage generator and the voltage input, receive the voltage input, and output a drive voltage. The main transistor of the electronic circuit may have a gate, a coupled to the drive voltage, and a drain coupled to a drain of the supplementary transistor.

Abstract translation: 提供了包括驱动器和主晶体管的电子电路。 驱动器可以包括偏置电压发生器，辅助晶体管和输出驱动器。 偏置电压发生器可以被配置为接收电压输入并且基于电压输入产生偏置电压输出。 辅助晶体管可以具有耦合到偏置电压发生器的偏置电压输出的栅极，以及向偏置电压发生器提供电流的辅助晶体管的源极。 输出驱动器可以被配置为接收来自偏置电压发生器和电压输入的偏置电压输出，接收电压输入并输出驱动电压。 电子电路的主晶体管可以具有耦合到驱动电压的栅极和耦合到辅助晶体管的漏极的漏极。

公开(公告)号：US20150137134A1

公开(公告)日：2015-05-21

申请号：US14083217

申请日：2013-11-18

Applicant: AVOGY, INC.

Inventor： Hemal N. Shah ,  Donald R. Disney

IPC: H01L29/20 ,  H01L23/00 ,  H01L23/36 ,  H01L27/06

CPC classification number: H01L29/2003 ,  H01L23/36 ,  H01L23/495 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/89 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/49111 ,  H01L2224/8384 ,  H01L2924/01322 ,  H01L2924/1033 ,  H01L2924/12032 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076

Abstract: An electronic package includes a leadframe and a plurality of pins. The electronic package also includes a first gallium nitride (GaN) transistor comprising a source, gate, and drain and a second GaN transistor comprising a source, gate, and drain. The source of the first GaN transistor is electrically connected to the leadframe and the drain of the second GaN transistor is electrically connected to the leadframe. The electronic package further includes a first GaN diode comprising an anode and cathode and a second GaN diode comprising an anode and cathode. The anode of the first GaN diode is electrically connected to the leadframe and the anode of the second GaN diode is electrically connected to the leadframe.

Abstract translation: 电子封装包括引线框和多个引脚。 电子封装还包括包括源极，栅极和漏极的第一氮化镓（GaN）晶体管和包括源极，栅极和漏极的第二GaN晶体管。 第一GaN晶体管的源极电连接到引线框架，并且第二GaN晶体管的漏极电连接到引线框架。 电子封装还包括包括阳极和阴极的第一GaN二极管和包括阳极和阴极的第二GaN二极管。 第一GaN二极管的阳极电连接到引线框架，并且第二GaN二极管的阳极电连接到引线框架。

公开(公告)号：US20150104912A1

公开(公告)日：2015-04-16

申请号：US14517564

申请日：2014-10-17

Applicant: Avogy, Inc.

Inventor： Donald R. Disney

IPC: H01L29/06 ,  H01L29/20 ,  H01L29/207 ,  H01L29/66

CPC classification number: H01L29/0619 ,  H01L21/26546 ,  H01L29/0615 ,  H01L29/0626 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/32 ,  H01L29/36 ,  H01L29/66143 ,  H01L29/66212 ,  H01L29/66909 ,  H01L29/66924 ,  H01L29/8083 ,  H01L29/8613 ,  H01L29/872

Abstract: A method for fabricating a vertical GaN power device includes providing a first GaN material having a first conductivity type and forming a second GaN material having a second conductivity type and coupled to the first GaN material to create a junction. The method further includes implanting ions through the second GaN material and into a first portion of the first GaN material to increase a doping concentration of the first conductivity type. The first portion of the junction is characterized by a reduced breakdown voltage relative to a breakdown voltage of a second portion of the junction.

Abstract translation: 制造垂直GaN功率器件的方法包括：提供具有第一导电类型的第一GaN材料，并形成具有第二导电类型的第二GaN材料并与第一GaN材料耦合以形成结。 该方法还包括将离子注入第二GaN材料并进入第一GaN材料的第一部分以增加第一导电类型的掺杂浓度。 结的第一部分的特征在于相对于结的第二部分的击穿电压降低的击穿电压。