中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

39 records (took 0.022 seconds)

    COHERENT BLOCK READ FULFILLMENT
    1.
    发明公开
    COHERENT BLOCK READ FULFILLMENT 审中-公开

    公开(公告)号：US20240202144A1

    公开(公告)日：2024-06-20

    申请号：US18410554

    申请日：2024-01-11

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Vydhyanathan Kalyanasundharam ,  Amit P. Apte ,  Eric Christopher Morton ,  Ganesh Balakrishnan ,  Ann M. Ling

    IPC: G06F13/16 ,  G06F3/06

    CPC classification number: G06F13/1673 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0679 ,  G06F2213/0038

    Abstract: A coherent memory fabric includes a plurality of coherent master controllers and a coherent slave controller. The plurality of coherent master controllers each include a response data buffer. The coherent slave controller is coupled to the plurality of coherent master controllers. The coherent slave controller, responsive to determining a selected coherent block read command is guaranteed to have only one data response, sends a target request globally ordered message to the selected coherent master controller and transmits responsive data. The selected coherent master controller, responsive to receiving the target request globally ordered message, blocks any coherent probes to an address associated with the selected coherent block read command until receipt of the responsive data is acknowledged by a requesting client.

    Region based split-directory scheme to adapt to large cache sizes
    3.
    发明授权
    Region based split-directory scheme to adapt to large cache sizes 有权

    公开(公告)号：US10705959B2

    公开(公告)日：2020-07-07

    申请号：US16119438

    申请日：2018-08-31

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Vydhyanathan Kalyanasundharam ,  Kevin M. Lepak ,  Amit P. Apte ,  Ganesh Balakrishnan

    IPC: G06F12/0817

    Abstract: Systems, apparatuses, and methods for maintaining region-based cache directories split between node and memory are disclosed. The system with multiple processing nodes includes cache directories split between the nodes and memory to help manage cache coherency among the nodes' cache subsystems. In order to reduce the number of entries in the cache directories, the cache directories track coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Each processing node includes a node-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the node. The node-based cache directory includes a reference count field in each entry to track the aggregate number of cache lines that are cached per region. The memory-based cache directory includes entries for regions which have an entry stored in any node-based cache directory of the system.

    CACHE TO CACHE DATA TRANSFER ACCELERATION TECHNIQUES
    5.
    发明申请
    CACHE TO CACHE DATA TRANSFER ACCELERATION TECHNIQUES 审中-公开

    公开(公告)号：US20190179758A1

    公开(公告)日：2019-06-13

    申请号：US15839662

    申请日：2017-12-12

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Vydhyanathan Kalyanasundharam ,  Amit P. Apte ,  Ganesh Balakrishnan ,  Ann Ling ,  Ravindra N. Bhargava

    IPC: G06F12/0862 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0831

    Abstract: Systems, apparatuses, and methods for accelerating cache to cache data transfers are disclosed. A system includes at least a plurality of processing nodes and prediction units, an interconnect fabric, and a memory. A first prediction unit is configured to receive memory requests generated by a first processing node as the requests traverse the interconnect fabric on the path to memory. When the first prediction unit receives a memory request, the first prediction unit generates a prediction of whether data targeted by the request is cached by another processing node. The first prediction unit is configured to cause a speculative probe to be sent to a second processing node responsive to predicting that the data targeted by the memory request is cached by the second processing node. The speculative probe accelerates the retrieval of the data from the second processing node if the prediction is correct.

    METHOD AND APPARATUS FOR ENCODING ERRONEOUS DATA IN AN ERROR CORRECTION CODE PROTECTED MEMORY
    6.
    发明申请
    METHOD AND APPARATUS FOR ENCODING ERRONEOUS DATA IN AN ERROR CORRECTION CODE PROTECTED MEMORY 有权
    在错误修正代码保护的存储器中编码错误数据的方法和装置

    公开(公告)号：US20150278016A1

    公开(公告)日：2015-10-01

    申请号：US14230115

    申请日：2014-03-31

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Ross V. La Fetra ,  Vilas K. Sridharan ,  Vydhyanathan Kalyanasundharam ,  Dean A. Liberty ,  Amit P. Apte

    IPC: G06F11/10

    CPC classification number: G06F11/1076 ,  G06F11/10 ,  G11B20/1833 ,  G11C29/52 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/0071 ,  H04L2027/0036

    Abstract: A method and device are described for encoding erroneous data in an error correction code (ECC) protected memory. In one embodiment, incoming data including a plurality of data symbols and a data integrity marker is received. At least one extra symbol is used to mark the incoming data as error-free data or erroneous data (i.e., poison) based on the data integrity marker. ECC may be created to protect the data symbols. The ECC may include a plurality of check symbols, a plurality of unused symbols and the at least one extra symbol. In another embodiment, an error marker may be propagated from a single ECC word to all ECC words of data block (e.g., a cache line, a page, and the like) to prevent errors due to corruption of the error marker caused by faulty memory in the erroneous ECC word.

    Abstract translation: 描述了用于对纠错码（ECC）保护存储器中的错误数据进行编码的方法和装置。 在一个实施例中，接收包括多个数据符号和数据完整性标记的输入数据。 使用至少一个额外的符号来将输入数据标记为基于数据完整性标记的无错误数据或错误数据（即毒药）。 可以创建ECC以保护数据符号。 ECC可以包括多个检查符号，多个未使用的符号和至少一个额外的符号。 在另一个实施例中，错误标记可以从单个ECC字传播到数据块的所有ECC字（例如，高速缓存线，页等），以防止由故障存储器引起的错误标记的损坏引起的错误 在错误的ECC字中。

    Region based split-directory scheme to adapt to large cache sizes
    7.
    发明授权
    Region based split-directory scheme to adapt to large cache sizes 有权

    公开(公告)号：US12158845B2

    公开(公告)日：2024-12-03

    申请号：US17721809

    申请日：2022-04-15

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Vydhyanathan Kalyanasundharam ,  Kevin M. Lepak ,  Amit P. Apte ,  Ganesh Balakrishnan

    IPC: G06F12/0817

    Abstract: Systems, apparatuses, and methods for maintaining region-based cache directories split between node and memory are disclosed. The system with multiple processing nodes includes cache directories split between the nodes and memory to help manage cache coherency among the nodes' cache subsystems. In order to reduce the number of entries in the cache directories, the cache directories track coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Each processing node includes a node-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the node. The node-based cache directory includes a reference count field in each entry to track the aggregate number of cache lines that are cached per region. The memory-based cache directory includes entries for regions which have an entry stored in any node-based cache directory of the system.

    PROBE FILTER RETENTION BASED LOW POWER STATE
    8.
    发明申请
    PROBE FILTER RETENTION BASED LOW POWER STATE 有权

    公开(公告)号：US20230039289A1

    公开(公告)日：2023-02-09

    申请号：US17973061

    申请日：2022-10-25

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Benjamin Tsien ,  Amit P. Apte

    IPC: G06F1/3228

    Abstract: A data fabric routes requests between the plurality of requestors and the plurality of responders. The data fabric includes a crossbar router, a coherent slave controller coupled to the crossbar router, and a probe filter coupled to the coherent slave controller and tracking the state of cached lines of memory. Power state control circuitry operates, responsive to detecting any of a plurality of designated conditions, to cause the probe filter to enter a retention low power state in which a clock signal to the probe filter is gated while power is maintained to the probe filter. Entering the retention low power state is performed when all in-process probe filter lookups are complete.

    DEMAND BASED PROBE FILTER INITIALIZATION AFTER LOW POWER STATE
    9.
    发明申请
    DEMAND BASED PROBE FILTER INITIALIZATION AFTER LOW POWER STATE 有权

    公开(公告)号：US20220413586A1

    公开(公告)日：2022-12-29

    申请号：US17357047

    申请日：2021-06-24

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Benjamin Tsien ,  Amit P. Apte

    IPC: G06F1/3234

    Abstract: A data fabric routes requests between the plurality of requestors. A probe filter tracks the state of cached lines of memory at a probe filter coupled to the data fabric. Responsive to the data fabric leaving a non-operational power state while all requestors that are probe filter clients are in a non-operational power state, the power management controller delays a probe filter initialization state in which data regarding cached lines is initialized following the non-operational power state.

    Probe filter retention based low power state
    10.
    发明授权
    Probe filter retention based low power state 有权

    公开(公告)号：US11487340B1

    公开(公告)日：2022-11-01

    申请号：US17357104

    申请日：2021-06-24

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Benjamin Tsien ,  Amit P. Apte

    IPC: G06F1/3228 ,  G06F13/26 ,  G06F12/0831 ,  G06F1/3296 ,  G06F1/3234

    Abstract: A data fabric routes requests between the plurality of requestors and the plurality of responders. The data fabric includes a crossbar router, a coherent slave controller coupled to the crossbar router, and a probe filter coupled to the coherent slave controller and tracking the state of cached lines of memory. Power state control circuitry operates, responsive to detecting any of a plurality of designated conditions, to cause the probe filter to enter a retention low power state in which a clock signal to the probe filter is gated while power is maintained to the probe filter. Entering the retention low power state is performed when all in-process probe filter lookups are complete.

Patent Agency Ranking