公开(公告)号：US20240319903A1

公开(公告)日：2024-09-26

申请号：US18187900

申请日：2023-03-22

Applicant: Advanced Micro Devices, Inc.

Inventor： William Robert Alverson ,  Jerry Anton Ahrens ,  Anil Harwani ,  Joshua Taylor Knight ,  Grant Evan Ley ,  Amitabh Mehra

IPC: G06F3/06

CPC classification number: G06F3/065 ,  G06F3/0619 ,  G06F3/0631 ,  G06F3/0683

Abstract: Duplicating memory content with chipset attached memory is described. In accordance with the described techniques, contents of a system memory are duplicated on a chipset attached memory over a chipset link. Memory requests are serviced using the contents of the system memory and the contents on the chipset attached memory. Servicing the memory requests includes servicing a first portion of a read request using the contents of the system memory and a second, remaining portion of the read request using the contents on the chipset attached memory. Servicing the memory requests further includes communicating a write request to the system memory and to the chipset attached memory.

公开(公告)号：US12038779B2

公开(公告)日：2024-07-16

申请号：US17704684

申请日：2022-03-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Amitabh Mehra ,  William Robert Alverson ,  Jerry Anton Ahrens ,  Grant Evan Ley ,  Anil Harwani ,  Joshua Taylor Knight

IPC: G06F1/00 ,  G06F1/08 ,  G06F1/20 ,  G06F1/30 ,  G06F1/324 ,  G06F1/3296

CPC classification number: G06F1/08 ,  G06F1/206 ,  G06F1/305 ,  G06F1/324 ,  G06F1/3296

Abstract: User configurable hardware settings for overclocking is described. In accordance with the described techniques, user input to adjust hardware settings for operating a processing unit in an overclocking mode is received. The user input, for example, adjusts at least one of a voltage droop threshold or a frequency adjustment of the clock rate. A voltage droop is detected while operating the processing unit in the overclocking mode. Responsive to detecting the voltage droop, a clock rate of the processing unit is adjusted based at least in part on the adjusted hardware settings.

公开(公告)号：US20240211160A1

公开(公告)日：2024-06-27

申请号：US18146929

申请日：2022-12-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Jerry Anton Ahrens ,  William Robert Alverson ,  Joshua Taylor Knight ,  Amitabh Mehra ,  Anil Harwani ,  Grant Evan Ley

IPC: G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/061 ,  G06F3/0658 ,  G06F3/0673 ,  G06F3/0683

Abstract: System memory training with chipset attached memory is described. In accordance with the described techniques, a request is received to train a system memory of a device. Responsive to the request, contents of the system memory are transferred to a chipset attached memory. The device is operated using the contents from the chipset attached memory. While the device is being operated using the contents from the chipset attached memory, the system memory is dynamically trained. After the training is complete, the contents are transferred back from the chipset attached memory to the trained system memory.

公开(公告)号：US20230350591A1

公开(公告)日：2023-11-02

申请号：US17732718

申请日：2022-04-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Grant Evan Ley ,  Jayesh Hari Joshi ,  Amitabh Mehra ,  Jerry Anton Ahrens ,  Joshua Taylor Knight ,  Anil Harwani ,  William Robert Alverson

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0613 ,  G06F3/0604 ,  G06F3/0673

Abstract: Profile switching for memory overclocking is described. In accordance with the described techniques, a memory is operated according to a first memory profile. During operation of the memory according to the first memory profile, a request is received to operate the memory according to a second memory profile. Responsive to the request, operation of the memory is switched to operate according to the second memory profile without rebooting. In one or more implementations, at least one of the first memory profile or the second memory profile comprises an overclocking memory profile that configures the memory to operate in an overclocking mode. In one or more implementations, the memory is trained to operate according to the overclocking memory profile prior to operating the memory according to the first memory profile.

公开(公告)号：US11747852B2

公开(公告)日：2023-09-05

申请号：US16726167

申请日：2019-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Amitabh Mehra ,  Jeffrey N. Burley ,  Anil Harwani

IPC: G06F1/08 ,  G06F11/30 ,  G06F1/26

CPC classification number: G06F1/08 ,  G06F1/26 ,  G06F11/3055 ,  G06F11/3058

Abstract: A method and apparatus for managing overclocking in a data center includes determining a frequency limit of a first processor of a first server in the data center. The voltage of the first processor is lowered to a stability point, and the frequency is lowered. The first server is tested for stability. Based upon the results of the test, the voltage and frequency modifications are deployed to a second processor of a second server in the data center.

公开(公告)号：US20240220208A1

公开(公告)日：2024-07-04

申请号：US18147257

申请日：2022-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Jerry Anton Ahrens ,  William Robert Alverson ,  Amitabh Mehra ,  Grant Evan Ley ,  Joshua Taylor Knight ,  Anil Harwani ,  Jayesh Hari Joshi

IPC: G06F7/58

CPC classification number: G06F7/588

Abstract: Induced signal marginality for random number generation is described. In accordance with the described techniques, a pseudorandom number is transmitted across an interface while the interface is operated with settings configured to cause instability in the interface. A random number is received as an output of the interface. The settings configured to cause instability in the interface include overclocked settings of interface operating parameters.

公开(公告)号：US20240211416A1

公开(公告)日：2024-06-27

申请号：US18146920

申请日：2022-12-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Jerry Anton Ahrens ,  William Robert Alverson ,  Joshua Taylor Knight ,  Amitabh Mehra ,  Anil Harwani ,  Grant Evan Ley

IPC: G06F13/16

CPC classification number: G06F13/1668 ,  G06F13/1626 ,  G06F13/1642

Abstract: Physical adjustment to system memory with chipset attached memory is described. In accordance with the described techniques, an indication for making one or more physical adjustments to system memory of a device is received. Contents of the system memory are transferred via a chipset link to a chipset attached memory. The device is operated using the contents from the chipset attached memory while the one or more physical adjustments are made to adjust the system memory. After the one or more physical adjustments, the contents are transferred back from the chipset attached memory to the adjusted system memory via the chipset link.

公开(公告)号：US20230350696A1

公开(公告)日：2023-11-02

申请号：US17732741

申请日：2022-04-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Anil Harwani ,  William Robert Alverson ,  Amitabh Mehra ,  Jerry Anton Ahrens ,  Grant Evan Ley ,  Joshua Taylor Knight

IPC: G06F9/445

CPC classification number: G06F9/44505

Abstract: Real time workload-based system adjustment is described. In accordance with the described techniques, a processor and a memory are operated according to first settings associated with a first workload. A second workload configured to utilize the processor and the memory is detected. The second workload is associated with second settings. Responsive to detecting the second workload, operation of the processor and the memory are adjusted to operate according to the second settings without rebooting.

公开(公告)号：US20230315191A1

公开(公告)日：2023-10-05

申请号：US17708453

申请日：2022-03-30

Applicant: Advanced Micro Devices, Inc.

Inventor： William Robert Alverson ,  Amitabh Mehra ,  Jerry Anton Ahrens ,  Grant Evan Ley ,  Anil Harwani ,  Joshua Taylor Knight

IPC: G06F1/3287 ,  G06F9/445 ,  G06F1/3206

CPC classification number: G06F1/3287 ,  G06F9/44505 ,  G06F1/3206

Abstract: Core activation and deactivation for a multi-core processor is described. In accordance with the described techniques, a processor having multiple cores operates using a first core configuration. A request to switch from the first core configuration to a second core configuration is received. Responsive to the request, a switch from the first core configuration to the second core configuration occurs by adjusting a number of active cores of the processor without rebooting.

公开(公告)号：US11740944B2

公开(公告)日：2023-08-29

申请号：US16711875

申请日：2019-12-12

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Amitabh Mehra ,  Anil Harwani ,  William Robert Alverson ,  Jerry Anton Ahrens, Jr. ,  Charles Sum Yuen Lee ,  John William Abshier

IPC: G06F1/324 ,  G06F9/50 ,  G06F9/4401 ,  G06F1/3287

CPC classification number: G06F9/5094 ,  G06F9/4403 ,  G06F1/324 ,  G06F1/3287

Abstract: A method and apparatus for managing processor functionality includes receiving, by the processor, data relating to one or more environmental conditions. The processor compares the data to pre-existing parameters to determine whether or not the environmental conditions are within the pre-existing parameters for normal operation. If the data are within the pre-existing parameters for normal operation, the processor is operated in a normal operation mode. If the data are outside the pre-existing parameters for normal operation, the processor operates in a second operation mode which is dynamically determined and calibrated during power-on, boot and operation.