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公开(公告)号：US12266030B2
公开(公告)日：2025-04-01
申请号：US17231425
申请日：2021-04-15
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Anirudh R. Acharya , Ruijin Wu , Young In Yeo
Abstract: Systems and methods related to priority-based and performance-based selection of a render mode, such as a two-level binning mode, in which to execute workloads with a graphics processing unit (GPU) of a system are provided. A user mode driver (UMD) or kernel mode driver (KMD) executed at a central processing unit (CPU) configures low and medium priority workloads to be executed in a two-level binning mode and selects a binning mode for high priority workloads based on whether performance heuristics indicate that one or more binning conditions or override conditions have been met. High priority workloads are maintained in a high priority queue, while low and medium priority workloads are maintained in a low/medium priority queue, such that execution of low and medium priority workloads at the GPU can be preempted in favor of executing high priority workloads.
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公开(公告)号：US20230055695A1
公开(公告)日：2023-02-23
申请号：US18045128
申请日：2022-10-07
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Anirudh R. Acharya , Michael J. Mantor , Rex Eldon McCrary , Anthony Asaro , Jeffrey Gongxian Cheng , Mark Fowler
Abstract: Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.
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公开(公告)号：US20210398325A1
公开(公告)日：2021-12-23
申请号：US17187625
申请日：2021-02-26
Applicant: Advanced Micro Devices, Inc.
Inventor： Kiia Kallio , Mika Tuomi , Ruijin Wu , Anirudh R. Acharya
Abstract: Methods, devices, and systems for compressing and decompressing a stream of indices associated with graphics primitives. A group of delta values is determined based on a group of indices of the stream of indices. The group of delta values is compared to delta values in a lookup table. The group of indices is compressed based on an entry in the lookup table if the group of delta values matches all delta values in the entry, otherwise, the group of indices is compressed based on variable-length encoding.
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公开(公告)号：US20210011760A1
公开(公告)日：2021-01-14
申请号：US16938381
申请日：2020-07-24
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Anirudh R. Acharya , Michael J. Mantor , Rex Eldon McCrary , Anthony Asaro , Jeffrey Gongxian Cheng , Mark Fowler
Abstract: Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.
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公开(公告)号：US12154224B2
公开(公告)日：2024-11-26
申请号：US17033023
申请日：2020-09-25
Applicant: Advanced Micro Devices, Inc.
Inventor： Jan H. Achrenius , Kiia Kallio , Miikka Kangasluoma , Ruijin Wu , Anirudh R. Acharya
Abstract: Some implementations provide systems, devices, and methods for rendering a plurality of primitives of a frame, the plurality of primitives being divided into a plurality of batches of primitives and the frame being divided into a plurality of bins. For at least one batch of the plurality of batches the rendering includes, for each of the plurality of bins, rendering primitives of a first sub-batch rasterizing to that bin, and for each of the plurality of bins, rendering primitives of a second sub-batch rasterizing to that bin.
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Patent Agency Ranking
公开(公告)号：US12051154B2
公开(公告)日：2024-07-30
申请号：US17562751
申请日：2021-12-27
Applicant: Advanced Micro Devices, Inc.
Inventor： Anirudh R. Acharya , Ruijin Wu
CPC classification number: G06T17/10 , G06T1/20 , G06T15/005 , G06T15/40
Abstract: Systems and methods for distributed rendering using two-level binning include processing primitives of a frame to be rendered at a first graphics processing unit (GPU) chiplet in a set of GPU chiplets to generate visibility information of primitives for each coarse bin and providing the visibility information to the other GPU chiplets in the set of GPU chiplets. Each coarse bin is then assigned to one of the GPU chiplets of the set of GPU chiplets and rendered at the assigned GPU chiplet based on the corresponding visibility information.
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公开(公告)号：US11579876B2
公开(公告)日：2023-02-14
申请号：US17008006
申请日：2020-08-31
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： Anirudh R. Acharya , Alexander Fuad Ashkar , Ashkan Hosseinzadeh Namin
Abstract: A method of save-restore operations includes monitoring, by a power controller of a parallel processor (such as a graphics processing unit), of a register bus for one or more register write signals. The power controller determines that a register write signal is addressed to a state register that is designated to be saved prior to changing a power state of the parallel processor from a first state to a second state having a lower level of energy usage. The power controller instructs a copy of data corresponding to the state register to be written to a local memory module of the parallel processor. Subsequently, the parallel processor receives a power state change signal and writes state register data saved at the local memory module to an off-chip memory prior to changing the power state of the parallel processor.
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公开(公告)号：US11562459B2
公开(公告)日：2023-01-24
申请号：US17128388
申请日：2020-12-21
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
IPC: G06F12/0804 , G06T1/60 , G06T1/20 , G06F12/0888 , G06F12/0806 , G09G5/39
Abstract: A graphics pipeline includes a cache having cache lines that are configured to store data used to process frames in a graphics pipeline. The graphics pipeline is implemented using a processor that processes frames for the graphics pipeline using data stored in the cache. The processor processes a first frame and writes back a dirty cache line from the cache to a memory concurrently with processing of the first frame. The dirty cache line is retained in the cache and marked as clean subsequent to being written back to the memory. In some cases, the processor generates a hint that indicates a priority for writing back the dirty cache line based on a read command occupancy at a system memory controller.
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公开(公告)号：US20220309729A1
公开(公告)日：2022-09-29
申请号：US17565394
申请日：2021-12-29
Applicant: Advanced Micro Devices, Inc.
Inventor： Ruijin Wu , Mika Tuomi , Paavo Sampo Ilmari Pessi , Anirudh R. Acharya
Abstract: A method of tiled rendering is provided which comprises dividing a frame to be rendered, into a plurality of tiles, receiving commands to execute a plurality of subpasses of the tiles and interleaving execution of same subpasses of multiple tiles of the frame. Interleaving execution of same subpasses of multiple tiles comprises executing a previously ordered first subpass of a second tile between execution of the previously ordered first subpass of a first tile and execution of a subsequently ordered second subpass of the first tile. The interleaving is performed, for example, by executing the plurality of subpasses in an order different from the order in which the commands to execute the plurality of subpasses are stored and issued. Alternatively, interleaving is performed by executing one or more subpasses as skip operations such that the plurality of subpasses are executed in the same order.
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公开(公告)号：US20200042348A1
公开(公告)日：2020-02-06
申请号：US16050948
申请日：2018-07-31
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Anirudh R. Acharya , Michael J. Mantor , Rex Eldon McCrary , Anthony Asaro , Jeffrey Gongxian Cheng , Mark Fowler
Abstract: Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.
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