公开(公告)号：US20220415378A1

公开(公告)日：2022-12-29

申请号：US17359446

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Arijit Banerjee ,  John J. Wuu ,  Russell Schreiber

IPC: G11C8/16 ,  G06F30/392 ,  G11C11/419 ,  G11C11/418

Abstract: An apparatus and method for providing efficient floor planning, power, and performance tradeoffs of memory accesses. Adjacent bit cells in a column of an array use a split read port such that the bit cells do not share a read bit line while sharing a write bit line. The adjacent bit cells include asymmetrical read access circuits that convey data stored by latch circuitry of a corresponding bit cell to a corresponding read bit line. The layout of adjacent bit cells provides a number of contacted gate pitches per bit cell that is less than a sum of the maximum number of metal gates in layout of each of the adjacent bit cells divided by the number of adjacent bit cells.

公开(公告)号：US20210407617A1

公开(公告)日：2021-12-30

申请号：US17027983

申请日：2020-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber ,  Keith A. Kasprak ,  Vance Threatt ,  James A. Wingfield ,  William A. Halliday ,  Srinivas R. Sathu ,  Arijit Banerjee

IPC: G11C29/44 ,  G11C29/12 ,  G11C7/12 ,  G06F12/0811

Abstract: An integrated circuit includes a memory core and a built-in self-test (BIST) controller. The memory core has an array of memory cells located at intersections of a plurality of word lines and a plurality of bit line pairs. The BIST controller is coupled to the memory core and has a mission mode and a built-in self-test mode. When in the mission mode, the BIST controller performs read and write accesses using precharge on demand. When in the built-in self-test mode, the BIST controller performs a floating bit line test by draining a voltage on true and complement bit lines of a selected bit line pair and subsequently precharging the true and complement bit lines of the selected bit line pair, before reading or writing data using the true and complement bit lines of the selected bit line pair.

公开(公告)号：US12073919B2

公开(公告)日：2024-08-27

申请号：US17359445

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Arijit Banerjee ,  John J. Wuu ,  Russell Schreiber

IPC: G11C8/16 ,  G06F30/392 ,  G11C11/418 ,  G11C11/419

CPC classification number: G11C8/16 ,  G06F30/392 ,  G11C11/418 ,  G11C11/419

Abstract: An apparatus and method for providing efficient floor planning, power, and performance tradeoffs of memory accesses. A dual read port and single write port memory bit cell uses two asymmetrical read access circuits for conveying stored data on two read bit lines. The two read bit lines are pre-charged to different voltage reference levels. The layout of the memory bit cell places the two read bit lines on an opposed edge from the single write bit line. The layout uses a dummy gate placed over both p-type diffusion and n-type diffusion between the edges. The layout has a same number of p-type transistors as n-type transistors despite using asymmetrical read access circuits. The layout also has a contacted gate pitch that is one more than the number of p-type transistors.

公开(公告)号：US12033721B2

公开(公告)日：2024-07-09

申请号：US17359446

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Arijit Banerjee ,  John J. Wuu ,  Russell Schreiber

IPC: G11C8/16 ,  G06F30/392 ,  G11C11/418 ,  G11C11/419

CPC classification number: G11C8/16 ,  G06F30/392 ,  G11C11/418 ,  G11C11/419

Abstract: An apparatus and method for providing efficient floor planning, power, and performance tradeoffs of memory accesses. Adjacent bit cells in a column of an array use a split read port such that the bit cells do not share a read bit line while sharing a write bit line. The adjacent bit cells include asymmetrical read access circuits that convey data stored by latch circuitry of a corresponding bit cell to a corresponding read bit line. The layout of adjacent bit cells provides a number of contacted gate pitches per bit cell that is less than a sum of the maximum number of metal gates in layout of each of the adjacent bit cells divided by the number of adjacent bit cells.

公开(公告)号：US20210158855A1

公开(公告)日：2021-05-27

申请号：US16692714

申请日：2019-11-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Arijit Banerjee ,  Russell Schreiber ,  Kyle Whittle

IPC: G11C11/4091 ,  G11C11/419 ,  G11C11/4074 ,  G11C7/10

Abstract: A read path for reading data from a memory includes a sense amplifier having data (SAT) and data complement (SAC) output nodes and a latch. The latch includes an input tri-state inverter including first and second PMOS transistors connected between VDD and an intermediate node, and first and second NMOS transistors connected between VSS and the intermediate node. A gate connection of the first PMOS and NMOS transistors is connected to the SAT node; a gate connection of the second PMOS transistor is connected to a sense amplifier enable complement input; and a gate connection of the second NMOS transistor is connected to a sense amplifier enable input. The latch also includes an output driver with an input connected to the intermediate node and an output connected to a data output node. The latch thus has two gate delays between the SAT node and the data output node.

公开(公告)号：US20220415377A1

公开(公告)日：2022-12-29

申请号：US17359445

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Arijit Banerjee ,  John J. Wuu ,  Russell Schreiber

IPC: G11C8/16 ,  G11C11/418 ,  G11C11/419 ,  G06F30/392

Abstract: An apparatus and method for providing efficient floor planning, power, and performance tradeoffs of memory accesses. A dual read port and single write port memory bit cell uses two asymmetrical read access circuits for conveying stored data on two read bit lines. The two read bit lines are pre-charged to different voltage reference levels. The layout of the memory bit cell places the two read bit lines on an opposed edge from the single write bit line. The layout uses a dummy gate placed over both p-type diffusion and n-type diffusion between the edges. The layout has a same number of p-type transistors as n-type transistors despite using asymmetrical read access circuits. The layout also has a contacted gate pitch that is one more than the number of p-type transistors.

公开(公告)号：US11264115B2

公开(公告)日：2022-03-01

申请号：US17027983

申请日：2020-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber ,  Keith A. Kasprak ,  Vance Threatt ,  James A. Wingfield ,  William A. Halliday ,  Srinivas R. Sathu ,  Arijit Banerjee

IPC: G11C29/44 ,  G11C29/12 ,  G11C7/12 ,  G06F12/0811

Abstract: An integrated circuit includes a memory core and a built-in self-test (BIST) controller. The memory core has an array of memory cells located at intersections of a plurality of word lines and a plurality of bit line pairs. The BIST controller is coupled to the memory core and has a mission mode and a built-in self-test mode. When in the mission mode, the BIST controller performs read and write accesses using precharge on demand. When in the built-in self-test mode, the BIST controller performs a floating bit line test by draining a voltage on true and complement bit lines of a selected bit line pair and subsequently precharging the true and complement bit lines of the selected bit line pair, before reading or writing data using the true and complement bit lines of the selected bit line pair.

公开(公告)号：US11227651B2

公开(公告)日：2022-01-18

申请号：US16692714

申请日：2019-11-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Arijit Banerjee ,  Russell Schreiber ,  Kyle Whittle

IPC: G11C7/00 ,  G11C11/4091 ,  G11C11/419 ,  G11C7/10 ,  G11C11/4074

Abstract: A read path for reading data from a memory includes a sense amplifier having data (SAT) and data complement (SAC) output nodes and a latch. The latch includes an input tri-state inverter including first and second PMOS transistors connected between VDD and an intermediate node, and first and second NMOS transistors connected between VSS and the intermediate node. A gate connection of the first PMOS and NMOS transistors is connected to the SAT node; a gate connection of the second PMOS transistor is connected to a sense amplifier enable complement input; and a gate connection of the second NMOS transistor is connected to a sense amplifier enable input. The latch also includes an output driver with an input connected to the intermediate node and an output connected to a data output node. The latch thus has two gate delays between the SAT node and the data output node.