公开(公告)号：US20180088858A1

公开(公告)日：2018-03-29

申请号：US15274777

申请日：2016-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Mitesh R. Meswani ,  Dibakar Gope ,  Sooraj Puthoor

IPC: G06F3/06 ,  G06F12/0804

CPC classification number: G06F3/0647 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0685 ,  G06F12/0246

Abstract: A processing apparatus is provided that includes NVRAM and one or more processors configured to process a first set and a second set of instructions according to a hierarchical processing scope and process a scoped persistence barrier residing in the program after the first instruction set and before the second instruction set. The barrier includes an instruction to cause first data to persist in the NVRAM before second data persists in the NVRAM. The first data results from execution of each of the first set of instructions processed according to the one hierarchical processing scope. The second data results from execution of each of the second set of instructions processed according to the one hierarchical processing scope. The processing apparatus also includes a controller configured to cause the first data to persist in the NVRAM before the second data persists in the NVRAM based on the scoped persistence barrier.

公开(公告)号：US20190286362A1

公开(公告)日：2019-09-19

申请号：US16432391

申请日：2019-06-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Mitesh R. Meswani ,  Dibakar Gope ,  Sooraj Puthoor

IPC: G06F3/06 ,  G06F12/02

Abstract: A processing apparatus is provided that includes NVRAM and one or more processors configured to process a first set and a second set of instructions according to a hierarchical processing scope and process a scoped persistence barrier residing in the program after the first instruction set and before the second instruction set. The barrier includes an instruction to cause first data to persist in the NVRAM before second data persists in the NVRAM. The first data results from execution of each of the first set of instructions processed according to the one hierarchical processing scope. The second data results from execution of each of the second set of instructions processed according to the one hierarchical processing scope. The processing apparatus also includes a controller configured to cause the first data to persist in the NVRAM before the second data persists in the NVRAM based on the scoped persistence barrier.

公开(公告)号：US11573724B2

公开(公告)日：2023-02-07

申请号：US16432391

申请日：2019-06-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Mitesh R. Meswani ,  Dibakar Gope ,  Sooraj Puthoor

IPC: G06F3/06 ,  G06F12/02

Abstract: A processing apparatus is provided that includes NVRAM and one or more processors configured to process a first set and a second set of instructions according to a hierarchical processing scope and process a scoped persistence barrier residing in the program after the first instruction set and before the second instruction set. The barrier includes an instruction to cause first data to persist in the NVRAM before second data persists in the NVRAM. The first data results from execution of each of the first set of instructions processed according to the one hierarchical processing scope. The second data results from execution of each of the second set of instructions processed according to the one hierarchical processing scope. The processing apparatus also includes a controller configured to cause the first data to persist in the NVRAM before the second data persists in the NVRAM based on the scoped persistence barrier.

公开(公告)号：US10324650B2

公开(公告)日：2019-06-18

申请号：US15274777

申请日：2016-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Mitesh R. Meswani ,  Dibakar Gope ,  Sooraj Puthoor

IPC: G06F3/06 ,  G06F12/02

Abstract: A processing apparatus is provided that includes NVRAM and one or more processors configured to process a first set and a second set of instructions according to a hierarchical processing scope and process a scoped persistence barrier residing in the program after the first instruction set and before the second instruction set. The barrier includes an instruction to cause first data to persist in the NVRAM before second data persists in the NVRAM. The first data results from execution of each of the first set of instructions processed according to the one hierarchical processing scope. The second data results from execution of each of the second set of instructions processed according to the one hierarchical processing scope. The processing apparatus also includes a controller configured to cause the first data to persist in the NVRAM before the second data persists in the NVRAM based on the scoped persistence barrier.