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    SYSTEM-WIDE LOW POWER MANAGEMENT
    1.
    发明申请
    SYSTEM-WIDE LOW POWER MANAGEMENT 有权

    公开(公告)号：US20210333860A1

    公开(公告)日：2021-10-28

    申请号：US17366423

    申请日：2021-07-02

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Benjamin Tsien ,  Greggory D. Donley ,  Bryan P. Broussard

    IPC: G06F1/3287 ,  G06F9/50 ,  G06F1/3209 ,  G06F1/3234 ,  G06F1/3296

    Abstract: Systems, apparatuses, and methods for performing efficient power management for a multi-node computing system are disclosed. A computing system includes multiple nodes. When power down negotiation is distributed, negotiation for system-wide power down occurs within a lower level of a node hierarchy prior to negotiation for power down occurring at a higher level of the node hierarchy. When power down negotiation is centralized, a given node combines a state of its clients with indications received on its downstream link and sends an indication on an upstream link based on the combining. Only a root node sends power down requests.

    Bandwidth matched scheduler
    2.
    发明授权
    Bandwidth matched scheduler 有权

    公开(公告)号：US10601723B2

    公开(公告)日：2020-03-24

    申请号：US15951844

    申请日：2018-04-12

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Alan Dodson Smith ,  Vydhyanathan Kalyanasundharam ,  Bryan P. Broussard ,  Greggory D. Donley ,  Chintan S. Patel

    IPC: H04L12/873 ,  H04L12/841 ,  H04L12/877 ,  H04L12/875 ,  H04L12/54 ,  H04L12/70

    Abstract: A computing system uses a memory for storing data, one or more clients for generating network traffic and a communication fabric with network switches. The network switches include centralized storage structures, rather than separate input and output storage structures. The network switches store particular metadata corresponding to received packets in a single, centralized collapsing queue where the age of the packets corresponds to a queue entry position. The payload data of the packets are stored in a separate memory, so the relatively large amount of data is not shifted during the lifetime of the packet in the network switch. The network switches select sparse queue entries in the collapsible queue, deallocate the selected queue entries, and shift remaining allocated queue entries toward a first end of the queue with a delay proportional to the radix of the network switches.

    RE-PURPOSING BYTE ENABLES AS CLOCK ENABLES FOR POWER SAVINGS
    4.
    发明申请
    RE-PURPOSING BYTE ENABLES AS CLOCK ENABLES FOR POWER SAVINGS 有权

    公开(公告)号：US20220103489A1

    公开(公告)日：2022-03-31

    申请号：US17548398

    申请日：2021-12-10

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Greggory D. Donley ,  Vydhyanathan Kalyanasundharam ,  Mark A. Silla ,  Ashwin Chincholi

    IPC: H04L12/947 ,  H04L12/717 ,  H04L12/931 ,  H04L29/08 ,  H04L29/06

    Abstract: Systems, apparatuses, and methods for efficient data transfer in a computing system are disclosed. A source generates packets to send across a communication fabric (or fabric) to a destination. The source generates partition enable signals for the partitions of payload data. The source negates an enable signal for a particular partition when the source determines the packet type indicates the particular partition should have an associated asserted enable signal in the packet, but the source also determines the particular partition includes a particular data pattern. Routing components of the fabric disable clock signals to storage elements assigned to store the particular partition. The destination inserts the particular data pattern for the particular partition in the payload data.

    Re-purposing byte enables as clock enables for power savings
    5.
    发明授权
    Re-purposing byte enables as clock enables for power savings 有权

    公开(公告)号：US11223575B2

    公开(公告)日：2022-01-11

    申请号：US16725901

    申请日：2019-12-23

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Greggory D. Donley ,  Vydhyanathan Kalyanasundharam ,  Mark A. Silla ,  Ashwin Chincholi

    IPC: H04L12/947 ,  H04L12/717 ,  H04L12/931 ,  H04L29/08 ,  H04L29/06

    Abstract: Systems, apparatuses, and methods for efficient data transfer in a computing system are disclosed. A source generates packets to send across a communication fabric (or fabric) to a destination. The source generates partition enable signals for the partitions of payload data. The source negates an enable signal for a particular partition when the source determines the packet type indicates the particular partition should have an associated asserted enable signal in the packet, but the source also determines the particular partition includes a particular data pattern. Routing components of the fabric disable clock signals to storage elements assigned to store the particular partition. The destination inserts the particular data pattern for the particular partition in the payload data.

    System-wide low power management
    6.
    发明授权
    System-wide low power management 有权

    公开(公告)号：US11054887B2

    公开(公告)日：2021-07-06

    申请号：US15856546

    申请日：2017-12-28

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Benjamin Tsien ,  Greggory D. Donley ,  Bryan P. Broussard

    IPC: G06F1/32 ,  G06F1/3287 ,  G06F9/50 ,  G06F1/3209 ,  G06F1/3234 ,  G06F1/3296

    Abstract: Systems, apparatuses, and methods for performing efficient power management for a multi-node computing system are disclosed. A computing system includes multiple nodes. When power down negotiation is distributed, negotiation for system-wide power down occurs within a lower level of a node hierarchy prior to negotiation for power down occurring at a higher level of the node hierarchy. When power down negotiation is centralized, a given node combines a state of its clients with indications received on its downstream link and sends an indication on an upstream link based on the combining. Only a root node sends power down requests.

    RE-PURPOSING BYTE ENABLES AS CLOCK ENABLES FOR POWER SAVINGS
    7.
    发明申请
    RE-PURPOSING BYTE ENABLES AS CLOCK ENABLES FOR POWER SAVINGS 有权

    公开(公告)号：US20210194827A1

    公开(公告)日：2021-06-24

    申请号：US16725901

    申请日：2019-12-23

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Greggory D. Donley ,  Vydhyanathan Kalyanasundharam ,  Mark A. Silla ,  Ashwin Chincholi

    IPC: H04L12/947 ,  H04L12/931 ,  H04L12/717 ,  H04L29/06 ,  H04L29/08

    Abstract: Systems, apparatuses, and methods for efficient data transfer in a computing system are disclosed. A source generates packets to send across a communication fabric (or fabric) to a destination. The source generates partition enable signals for the partitions of payload data. The source negates an enable signal for a particular partition when the source determines the packet type indicates the particular partition should have an associated asserted enable signal in the packet, but the source also determines the particular partition includes a particular data pattern. Routing components of the fabric disable clock signals to storage elements assigned to store the particular partition. The destination inserts the particular data pattern for the particular partition in the payload data.

    LINK LAYER DATA PACKING AND PACKET FLOW CONTROL SCHEME
    8.
    发明申请
    LINK LAYER DATA PACKING AND PACKET FLOW CONTROL SCHEME 审中-公开

    公开(公告)号：US20200059437A1

    公开(公告)日：2020-02-20

    申请号：US16105367

    申请日：2018-08-20

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Greggory D. Donley ,  Bryan P. Broussard ,  Vydhyanathan Kalyanasundharam

    IPC: H04L12/865

    Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple fabric interfaces in clients and a fabric. A packet transmitter in the fabric interface includes multiple queues, each for storing packets of a respective type. The packet transmitter includes multiple queue arbiters, each for selecting a candidate packet from a respective one of the multiple queues. The packet transmitter includes a buffer for storing a link packet, which includes data storage space for storing multiple candidate packets. The packet transmitter selects qualified candidate packets from the multiple queues and inserts these candidate packets into the link packet. The packing arbiter avoids data collisions at the receiver by taking into consideration mismatches between the rate of inserting candidate packets into the link packet and the rate of creating available data storage space in a receiving queue in the receiver.

    BANDWIDTH MATCHED SCHEDULER
    9.
    发明申请
    BANDWIDTH MATCHED SCHEDULER 审中-公开

    公开(公告)号：US20190319891A1

    公开(公告)日：2019-10-17

    申请号：US15951844

    申请日：2018-04-12

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Alan Dodson Smith ,  Vydhyanathan Kalyanasundharam ,  Bryan P. Broussard ,  Greggory D. Donley ,  Chintan S. Patel

    IPC: H04L12/873 ,  H04L12/877 ,  H04L12/841 ,  H04L12/875

    Abstract: A computing system uses a memory for storing data, one or more clients for generating network traffic and a communication fabric with network switches. The network switches include centralized storage structures, rather than separate input and output storage structures. The network switches store particular metadata corresponding to received packets in a single, centralized collapsing queue where the age of the packets corresponds to a queue entry position. The payload data of the packets are stored in a separate memory, so the relatively large amount of data is not shifted during the lifetime of the packet in the network switch. The network switches select sparse queue entries in the collapsible queue, deallocate the selected queue entries, and shift remaining allocated queue entries toward a first end of the queue with a delay proportional to the radix of the network switches.

    SYSTEM-WIDE LOW POWER MANAGEMENT
    10.
    发明申请
    SYSTEM-WIDE LOW POWER MANAGEMENT 审中-公开

    公开(公告)号：US20190204899A1

    公开(公告)日：2019-07-04

    申请号：US15856546

    申请日：2017-12-28

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Benjamin Tsien ,  Greggory D. Donley ,  Bryan P. Broussard

    IPC: G06F1/32

    CPC classification number: G06F1/3287 ,  G06F1/3234 ,  G06F1/3296 ,  G06F9/5094

    Abstract: Systems, apparatuses, and methods for performing efficient power management for a multi-node computing system are disclosed. A computing system includes multiple nodes. When power down negotiation is distributed, negotiation for system-wide power down occurs within a lower level of a node hierarchy prior to negotiation for power down occurring at a higher level of the node hierarchy. When power down negotiation is centralized, a given node combines a state of its clients with indications received on its downstream link and sends an indication on an upstream link based on the combining. Only a root node sends power down requests.

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