公开(公告)号：US20240411692A1

公开(公告)日：2024-12-12

申请号：US18332112

申请日：2023-06-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel Hsiuwei Loh ,  Joseph Lee Greathouse ,  William Louie Walker ,  Paul James Moyer

IPC: G06F12/0802

Abstract: Cache replacement policies are described. In accordance with the described techniques, a request for data is received and a cache replacement policy controls how a controller responds to the request. The cache replacement policy assigns each cacheline a priority value, which indicates whether the cacheline should be preserved relative to other cachelines, in response to the request being a cache miss that necessitates eviction of at least one cacheline. The cache replacement policy decrements priority values until at least one cacheline achieves a minimum priority value, at which point a cacheline is evicted. The cache replacement policy designates certain cachelines as protected, either via a separate protected indicator or via the cacheline's priority value, which causes unprotected cachelines to be selected for eviction while favoring preservation of protected cachelines in the cache.

公开(公告)号：US20220100686A1

公开(公告)日：2022-03-31

申请号：US17548385

申请日：2021-12-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Eric Christopher Morton ,  Bryan P. Broussard ,  Paul James Moyer ,  William Louie Walker

IPC: G06F13/24 ,  G06F13/42

Abstract: Systems, apparatuses, and methods for routing interrupts on a coherency probe network are disclosed. A computing system includes a plurality of processing nodes, a coherency probe network, and one or more control units. The coherency probe network carries coherency probe messages between coherent agents. Interrupts that are detected by a control unit are converted into messages that are compatible with coherency probe messages and then routed to a target destination via the coherency probe network. Interrupts are generated with a first encoding while coherency probe messages have a second encoding. Cache subsystems determine whether a message received via the coherency probe network is an interrupt message or a coherency probe message based on an encoding embedded in the received message. Interrupt messages are routed to interrupt controller(s) while coherency probe messages are processed in accordance with a coherence probe action field embedded in the message.

公开(公告)号：US10922230B2

公开(公告)日：2021-02-16

申请号：US15211547

申请日：2016-07-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul James Moyer

IPC: G06F12/08 ,  G06F12/10 ,  G06F12/0844 ,  G06F12/0895 ,  G06F12/0868 ,  G06F12/1027 ,  G06F12/0831 ,  G06F12/0811

Abstract: A processing system indicates the pendency of a memory access request for data at the cache entry that is assigned to store the data in response to the memory access request. While executing instructions, the processor issues requests for data to the cache most proximal to the processor. In response to a cache miss, the cache controller identifies an entry of the cache to store the data in response to the memory access request, and stores an indication that the memory access request is pending at the identified cache entry. If the cache controller receives a subsequent memory access request for the data while the memory access request is pending at the higher level of the memory hierarchy, the cache controller identifies that the memory access request is pending based on the indicator stored at the entry.

公开(公告)号：US12026099B2

公开(公告)日：2024-07-02

申请号：US17181879

申请日：2021-02-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Paul James Moyer

IPC: G06F12/0895 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0866 ,  G06F12/0897

CPC classification number: G06F12/0895 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/0897 ,  G06F12/0815 ,  G06F2212/1016 ,  G06F2212/1028

Abstract: A cache stores, along with data that is being transferred from a higher level cache to a lower level cache, information indicating the higher level cache location from which the data was transferred. Upon receiving a request for data that is stored at the location in the higher level cache, a cache controller stores the higher level cache location information in a status tag of the data. The cache controller then transfers the data with the status tag indicating the higher level cache location to a lower level cache. When the data is subsequently updated or evicted from the lower level cache, the cache controller reads the status tag location information and transfers the data back to the location in the higher level cache from which it was originally transferred.

公开(公告)号：US10339063B2

公开(公告)日：2019-07-02

申请号：US15213981

申请日：2016-07-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul James Moyer ,  Richard Martin Born

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/0877 ,  G06F9/38

Abstract: A processor includes an operations scheduler to schedule execution of operations at, for example, a set of execution units or a cache of the processor. The operations scheduler periodically adds sets of operations to a tracking array, and further identifies when an operation in the tracked set is blocked from execution scheduling in response to, for example, identifying that the operation is dependent on another operation that has not completed execution. The processor further includes a counter that is adjusted each time an operation in the tracking array is blocked from execution, and is reset each time an operation in the tracking array is executed. When the value of the counter exceeds a threshold, the operations scheduler prioritizes the remaining tracked operations for execution scheduling.

公开(公告)号：US09928176B2

公开(公告)日：2018-03-27

申请号：US15215033

申请日：2016-07-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul James Moyer

IPC: G06F12/08 ,  G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/6026

Abstract: A processor applies a transfer policy to a portion of a cache based on access metrics for different test regions of the cache, wherein each test region applies a different transfer policy for data in cache entries that were stored in response to a prefetch requests but were not the subject of demand requests. One test region applies a transfer policy under which unused prefetches are transferred to a higher level cache in a cache hierarchy upon eviction from the test region of the cache. The other test region applies a transfer policy under which unused prefetches are replaced without being transferred to a higher level cache (or are transferred to the higher level cache but stored as invalid data) upon eviction from the test region of the cache.

公开(公告)号：US20180024934A1

公开(公告)日：2018-01-25

申请号：US15213981

申请日：2016-07-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul James Moyer ,  Richard Martin Born

IPC: G06F12/0877

CPC classification number: G06F12/0877 ,  G06F9/3836 ,  G06F9/3855 ,  G06F2212/60

Abstract: A processor includes an operations scheduler to schedule execution of operations at, for example, a set of execution units or a cache of the processor. The operations scheduler periodically adds sets of operations to a tracking array, and further identifies when an operation in the tracked set is blocked from execution scheduling in response to, for example, identifying that the operation is dependent on another operation that has not completed execution. The processor further includes a counter that is adjusted each time an operation in the tracking array is blocked from execution, and is reset each time an operation in the tracking array is executed. When the value of the counter exceeds a threshold, the operations scheduler prioritizes the remaining tracked operations for execution scheduling.

公开(公告)号：US20170357446A1

公开(公告)日：2017-12-14

申请号：US15180807

申请日：2016-06-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul James Moyer

IPC: G06F3/06 ,  G06F12/0891 ,  G06F12/0897

CPC classification number: G06F12/0897 ,  G06F12/0891 ,  G06F12/128 ,  G06F2212/1016 ,  G06F2212/1028 ,  Y02D10/13

Abstract: A processing system selects entries for eviction at one cache based at least in part on the validity status of corresponding entries at a different cache. The processing system includes a memory hierarchy having at least two caches, a higher level cache and a lower level cache. The lower level cache monitors which locations of the higher level cache have been indicated as invalid and, when selecting an entry of the lower level cache for eviction to the higher level cache, selects the entry based at least in part on whether the selected cache entry will be stored at an invalid cache line of the higher level cache.

公开(公告)号：US11669457B2

公开(公告)日：2023-06-06

申请号：US17459100

申请日：2021-08-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul James Moyer ,  Douglas Benson Hunt

IPC: G06F12/0891 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0811

CPC classification number: G06F12/0891 ,  G06F9/3009 ,  G06F9/3816 ,  G06F12/0811

Abstract: Systems, apparatuses, and methods for generating a measurement of write memory bandwidth are disclosed. A control unit monitors writes to a cache hierarchy. If a write to a cache line is a first time that the cache line is being modified since entering the cache hierarchy, then the control unit increments a write memory bandwidth counter. Otherwise, if the write is to a cache line that has already been modified since entering the cache hierarchy, then the write memory bandwidth counter is not incremented. The first write to a cache line is a proxy for write memory bandwidth since this will eventually cause a write to memory. The control unit uses the value of the write memory bandwidth counter to generate a measurement of the write memory bandwidth. Also, the control unit can maintain multiple counters for different thread classes to calculate the write memory bandwidth per thread class.

公开(公告)号：US20220058025A1

公开(公告)日：2022-02-24

申请号：US17519902

申请日：2021-11-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul James Moyer ,  Douglas Benson Hunt ,  Kai Troester

IPC: G06F9/38

Abstract: Systems, apparatuses, and methods for arbitrating threads in a computing system are disclosed. A computing system includes a processor with multiple cores, each capable of simultaneously processing instructions of multiple threads. When a thread throttling unit receives an indication that a shared cache has resource contention, the throttling unit sets a threshold number of cache misses for the cache. If the number of cache misses exceeds this threshold, then the throttling unit notifies a particular upstream computation unit to throttle the processing of instructions for the thread. After a time period elapses, if the cache continues to exceed the threshold, then the throttling unit notifies the upstream computation unit to more restrictively throttle the thread by performing one or more of reducing the selection rate and increasing the time period. Otherwise, the unit notifies the upstream computation unit to less restrictively throttle the thread.