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    Managing frequency changes of clock signals across different clock domains
    2.
    发明授权
    Managing frequency changes of clock signals across different clock domains 有权

    公开(公告)号：US10168731B2

    公开(公告)日：2019-01-01

    申请号：US15209521

    申请日：2016-07-13

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Steven Kommrusch ,  Amitabh Mehra ,  Richard Martin Born

    IPC: G06F1/26 ,  G06F1/00 ,  G06F1/32 ,  G06F1/08 ,  G06F13/14

    Abstract: A processor maintains a minimum setup time for data being transferred between clock domains, including maintaining the minimum setup time in response to a frequency change in a clock signal for at least one of the clock domains. The processor employs one or more control modules that monitor clock edges in each of the clock domains to ensure that data is not accessed by the receiving clock domain from a storage location until a minimum number of phases have elapsed in the transferring clock domain after the data has been written to the storage location. Further, the control module maintains the minimum setup time in response to a change in clock frequency at one or both of the clock domains.

    Apparatus and methods employing asynchronous FIFO buffer with read prediction
    6.
    发明授权
    Apparatus and methods employing asynchronous FIFO buffer with read prediction 有权

    公开(公告)号：US12176064B2

    公开(公告)日：2024-12-24

    申请号：US17559131

    申请日：2021-12-22

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Richard Martin Born ,  David M. Dahle

    IPC: G11C7/22 ,  G06F5/06 ,  G11C7/10

    Abstract: Methods and apparatus employ an asynchronous first-in-first-out buffer (FIFO), that includes a plurality of entries. Control logic determines a timing separation between a write header valid signal and corresponding write data valid signal for a write operation to an entry in the first-in-first-out buffer (FIFO) and performs a read of the corresponding data from the entry in the FIFO in the second clock domain, based on the determined timing separation of the write header valid signal and corresponding write data valid signal, and based on a clock frequency ratio between the first and second clock domains.

    Asynchronous buffer with pointer offsets
    8.
    发明授权
    Asynchronous buffer with pointer offsets 有权

    公开(公告)号：US10592442B2

    公开(公告)日：2020-03-17

    申请号：US15837951

    申请日：2017-12-11

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Richard Martin Born ,  David M. Dahle ,  Steven Kommrusch

    IPC: G06F13/16 ,  G06F5/14 ,  G06F13/42

    Abstract: A processor applies offset values to read and write pointers to a first-in-first-out buffer (FIFO) for data being transferred between clock domains. The pointer offsets are based on a frequency ratio between the clock domains, and reduce latency while ensuring that data is not read by the receiving clock domain from an entry of the FIFO until after the data has been written to the entry, thereby reducing data transfer errors. The processor resets the pointer offset values in response to a change in clock frequency at one or both of the clock domains, allowing the processor to continue to accurately transfer data in response to clock frequency changes.

    Scheduling independent and dependent operations for processing
    9.
    发明授权
    Scheduling independent and dependent operations for processing 有权

    公开(公告)号：US10339063B2

    公开(公告)日：2019-07-02

    申请号：US15213981

    申请日：2016-07-19

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Paul James Moyer ,  Richard Martin Born

    IPC: G06F12/00 ,  G06F13/00 ,  G06F12/0877 ,  G06F9/38

    Abstract: A processor includes an operations scheduler to schedule execution of operations at, for example, a set of execution units or a cache of the processor. The operations scheduler periodically adds sets of operations to a tracking array, and further identifies when an operation in the tracked set is blocked from execution scheduling in response to, for example, identifying that the operation is dependent on another operation that has not completed execution. The processor further includes a counter that is adjusted each time an operation in the tracking array is blocked from execution, and is reset each time an operation in the tracking array is executed. When the value of the counter exceeds a threshold, the operations scheduler prioritizes the remaining tracked operations for execution scheduling.

    SCHEDULING INDEPENDENT AND DEPENDENT OPERATIONS FOR PROCESSING
    10.
    发明申请
    SCHEDULING INDEPENDENT AND DEPENDENT OPERATIONS FOR PROCESSING 审中-公开

    公开(公告)号：US20180024934A1

    公开(公告)日：2018-01-25

    申请号：US15213981

    申请日：2016-07-19

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Paul James Moyer ,  Richard Martin Born

    IPC: G06F12/0877

    CPC classification number: G06F12/0877 ,  G06F9/3836 ,  G06F9/3855 ,  G06F2212/60

    Abstract: A processor includes an operations scheduler to schedule execution of operations at, for example, a set of execution units or a cache of the processor. The operations scheduler periodically adds sets of operations to a tracking array, and further identifies when an operation in the tracked set is blocked from execution scheduling in response to, for example, identifying that the operation is dependent on another operation that has not completed execution. The processor further includes a counter that is adjusted each time an operation in the tracking array is blocked from execution, and is reset each time an operation in the tracking array is executed. When the value of the counter exceeds a threshold, the operations scheduler prioritizes the remaining tracked operations for execution scheduling.

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