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    Processing system with selective priority-based two-level binning
    1.
    发明授权
    Processing system with selective priority-based two-level binning 有权

    公开(公告)号：US12266030B2

    公开(公告)日：2025-04-01

    申请号：US17231425

    申请日：2021-04-15

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Anirudh R. Acharya ,  Ruijin Wu ,  Young In Yeo

    IPC: G06T1/20 ,  G06F9/50 ,  G06T7/11

    Abstract: Systems and methods related to priority-based and performance-based selection of a render mode, such as a two-level binning mode, in which to execute workloads with a graphics processing unit (GPU) of a system are provided. A user mode driver (UMD) or kernel mode driver (KMD) executed at a central processing unit (CPU) configures low and medium priority workloads to be executed in a two-level binning mode and selects a binning mode for high priority workloads based on whether performance heuristics indicate that one or more binning conditions or override conditions have been met. High priority workloads are maintained in a high priority queue, while low and medium priority workloads are maintained in a low/medium priority queue, such that execution of low and medium priority workloads at the GPU can be preempted in favor of executing high priority workloads.

    Active bridge chiplet with integrated cache
    3.
    发明授权
    Active bridge chiplet with integrated cache 有权

    公开(公告)号：US11507527B2

    公开(公告)日：2022-11-22

    申请号：US16585452

    申请日：2019-09-27

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Skyler J. Saleh ,  Ruijin Wu

    IPC: G06F13/40 ,  G06T1/20 ,  G06F12/0815

    Abstract: A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via an active bridge chiplet. The active bridge chiplet is an active silicon die that bridges GPU chiplets and allows partitioning of systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.

    Data flow in a distributed graphics processing unit architecture
    4.
    发明授权
    Data flow in a distributed graphics processing unit architecture 有权

    公开(公告)号：US11232622B2

    公开(公告)日：2022-01-25

    申请号：US16698624

    申请日：2019-11-27

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Skyler J. Saleh ,  Ruijin Wu

    IPC: G06T15/00 ,  G06T1/20 ,  G06F9/54

    Abstract: An apparatus includes a command buffer configured to temporarily store commands. The apparatus also includes processing units disposed at a substrate. The processing units are configured to access a plurality of copies of a command from the command buffer. The processing units include first processing units (such as fixed function hardware blocks) to perform geometry operations indicated by the command on a set of primitives. The geometry operations are performed concurrently by the first processing units. The processing units also include second processing units (such as shaders) to process mutually exclusive sets of pixels generated by rasterizing the set of primitives. The apparatus also includes a cache to temporarily store the pixels after shading by the shaders. The processing units stop or interrupt processing commands in response to detecting a synchronization point and resume processing the commands in response to all the processing units completing commands before synchronization point.

    METHOD AND SYSTEM FOR DEPTH PRE-PROCESSING AND GEOMETRY SORTING USING BINNING HARDWARE
    7.
    发明申请
    METHOD AND SYSTEM FOR DEPTH PRE-PROCESSING AND GEOMETRY SORTING USING BINNING HARDWARE 审中-公开

    公开(公告)号：US20200098169A1

    公开(公告)日：2020-03-26

    申请号：US16137830

    申请日：2018-09-21

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Ruijin Wu ,  Young In Yeo ,  Sagar S. Bhandare ,  Vineet Goel ,  Martin G. Sarov ,  Christopher J. Brennan

    IPC: G06T15/80 ,  G06T15/00 ,  G06T1/20

    Abstract: Described herein are techniques for improving the effectiveness of depth culling. In a first technique, a binner is used to sort primitives into depth bins. Each depth bin covers a range of depths. The binner transmits the depth bins to the screen space pipeline for processing in near-to-far order. Processing the near bins first results in the depth buffer being updated, allowing fragments for the primitives in the farther bins to be culled more aggressively than if the depth binning did not occur. In a second technique, a buffer is used to initiate two-pass processing through the screen space pipeline. In the first pass, primitives are sent down to update the depth block and are then culled. The fragments are processed normally in the second pass, with the benefit of the updated depth values.

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