公开(公告)号：US20220012933A1

公开(公告)日：2022-01-13

申请号：US17483678

申请日：2021-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Skyler Jonathon Saleh ,  Vineet Goel ,  Pazhani Pillai ,  Ruijin Wu ,  Christopher J. Brennan ,  Andrew S. Pomianowski

IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60

Abstract: Techniques for performing shader operations are provided. The techniques include, performing pixel shading at a shading rate defined by pixel shader variable rate shading (“VRS”) data, and updating the pixel VRS data that indicates one or more shading rates for one or more tiles based on whether the tiles of the one or more tiles include triangle edges or do not include triangle edges, to generate updated VRS data.

公开(公告)号：US20210150669A1

公开(公告)日：2021-05-20

申请号：US16687569

申请日：2019-11-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander M. Potapov ,  Skyler Jonathon Saleh ,  Swapnil P. Sakharshete ,  Vineet Goel

IPC: G06T3/40

Abstract: A processing device is provided which includes memory and a processor. The processor is configured to receive an input image having a first resolution, generate linear down-sampled versions of the input image by down-sampling the input image via a linear upscaling network and generate non-linear down-sampled versions of the input image by down-sampling the input image via a non-linear upscaling network. The processor is also configured to convert the down-sampled versions of the input image into pixels of an output image having a second resolution higher than the first resolution and provide the output image for display

公开(公告)号：US20200098169A1

公开(公告)日：2020-03-26

申请号：US16137830

申请日：2018-09-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Ruijin Wu ,  Young In Yeo ,  Sagar S. Bhandare ,  Vineet Goel ,  Martin G. Sarov ,  Christopher J. Brennan

IPC: G06T15/80 ,  G06T15/00 ,  G06T1/20

Abstract: Described herein are techniques for improving the effectiveness of depth culling. In a first technique, a binner is used to sort primitives into depth bins. Each depth bin covers a range of depths. The binner transmits the depth bins to the screen space pipeline for processing in near-to-far order. Processing the near bins first results in the depth buffer being updated, allowing fragments for the primitives in the farther bins to be culled more aggressively than if the depth binning did not occur. In a second technique, a buffer is used to initiate two-pass processing through the screen space pipeline. In the first pass, primitives are sent down to update the depth block and are then culled. The fragments are processed normally in the second pass, with the benefit of the updated depth values.

公开(公告)号：US10600142B2

公开(公告)日：2020-03-24

申请号：US15832131

申请日：2017-12-05

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Usame Ceylan ,  Young In Yeo ,  Todd Martin ,  Vineet Goel

IPC: G06T9/00 ,  G06T1/20 ,  G06T15/00 ,  G06T11/00

Abstract: A compute unit accesses a chunk of bits that represent indices of vertices of a graphics primitive. The compute unit sets values of a first bit to indicate whether the chunk is monotonic or ordinary, second bits to define an offset that is determined based on values of indices in the chunk, and sets of third bits that determine values of the indices in the chunk based on the offset defined by the second bits. The compute unit writes a compressed chunk represented by the first bit, the second bits, and the sets of third bits to a memory. The compressed chunk is decompressed and the decompressed indices are written to an index buffer. In some embodiments, the indices are decompressed based on metadata that includes offsets that are determined based on values of the indices and bitfields that indicate characteristics of the indices.

公开(公告)号：US20230252713A1

公开(公告)日：2023-08-10

申请号：US18304115

申请日：2023-04-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Skyler Jonathon Saleh ,  Vineet Goel ,  Pazhani Pillai ,  Ruijin Wu ,  Christopher J. Brennan ,  Andrew S. Pomianowski

IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06T15/005 ,  G06T1/20 ,  G06T1/60 ,  G06T2210/52

Abstract: Techniques for performing shader operations are provided. The techniques include, performing pixel shading at a shading rate defined by pixel shader variable rate shading (“VRS”) data, and updating the pixel VRS data that indicates one or more shading rates for one or more tiles based on whether the tiles of the one or more tiles include triangle edges or do not include triangle edges, to generate updated VRS data.

公开(公告)号：US11657560B2

公开(公告)日：2023-05-23

申请号：US17483678

申请日：2021-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Skyler Jonathon Saleh ,  Vineet Goel ,  Pazhani Pillai ,  Ruijin Wu ,  Christopher J. Brennan ,  Andrew S. Pomianowski

IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06T15/005 ,  G06T1/20 ,  G06T1/60 ,  G06T2210/52

Abstract: Techniques for performing shader operations are provided. The techniques include, performing pixel shading at a shading rate defined by pixel shader variable rate shading (“VRS”) data, and updating the pixel VRS data that indicates one or more shading rates for one or more tiles based on whether the tiles of the one or more tiles include triangle edges or do not include triangle edges, to generate updated VRS data.

公开(公告)号：US11657119B2

公开(公告)日：2023-05-23

申请号：US16557911

申请日：2019-08-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Swapnil P. Sakharshete ,  Samuel Lawrence Wasmundt ,  Maxim V. Kazakov ,  Vineet Goel

IPC: G06F17/16 ,  G06N3/08

CPC classification number: G06F17/16 ,  G06N3/08

Abstract: A processing device is provided which includes memory configured to store data and a processor configured to determine, based on convolutional parameters associated with an image, a virtual general matrix-matrix multiplication (GEMM) space of a virtual GEMM space output matrix and generate, in the virtual GEMM space output matrix, a convolution result by matrix multiplying the data corresponding to a virtual GEMM space input matrix with the data corresponding to a virtual GEMM space filter matrix. The processing device also includes convolutional mapping hardware configured to map, based on the convolutional parameters, positions of the virtual GEMM space input matrix to positions of an image space of the image.

公开(公告)号：US20210225060A1

公开(公告)日：2021-07-22

申请号：US17033259

申请日：2020-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Mika Tuomi ,  Kiia Kallio ,  Ruijin Wu ,  Anirudh R. Acharya ,  Vineet Goel

IPC: G06T15/00 ,  G06T15/08 ,  G06T1/20

Abstract: A processing device and a method of tiled rendering of an image for display is provided. The processing device includes memory and a processor. The processor is configured to receive the image comprising one or more three dimensional (3D) objects, divide the image into tiles, execute coarse level tiling for the tiles of the image and execute fine level tiling for the tiles of the image. The processing device also includes same fixed function hardware used to execute the coarse level tiling and the fine level tiling. The processor is also configured to determine visibility information for a first one of the tiles. The visibility information is divided into draw call visibility information and triangle visibility information for each remaining tile of the image.

公开(公告)号：US20210089423A1

公开(公告)日：2021-03-25

申请号：US16913562

申请日：2020-06-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Ruijin Wu ,  Skyler Jonathon Saleh ,  Vineet Goel

IPC: G06F11/34 ,  G06F9/54 ,  G06F15/82

Abstract: A technique for operating a processor that includes multiple cores is provided. The technique includes determining a number of active applications, selecting a processor configuration for the processor based on the number of active applications, configuring the processor according to the selected processor configuration, and executing the active applications with the configured processor.

公开(公告)号：US10210650B1

公开(公告)日：2019-02-19

申请号：US15828055

申请日：2017-11-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anirudh R. Acharya ,  Swapnil Sakharshete ,  Michael Mantor ,  Mangesh P. Nijasure ,  Todd Martin ,  Vineet Goel

IPC: G06T15/00 ,  G06T1/20 ,  G06T15/80 ,  G06F9/48 ,  G06F9/50

Abstract: Processing of non-real-time and real-time workloads is performed using discrete pipelines. A first pipeline includes a first shader and one or more fixed function hardware blocks. A second pipeline includes a second shader that is configured to emulate the at least one fixed function hardware block. First and second memory elements store first state information for the first pipeline and second state information for the second pipeline, respectively. A non-real-time workload executing in the first pipeline is preempted at a primitive boundary in response to a real-time workload being dispatched for execution in the second pipeline. The first memory element retains the first state information in response to preemption of the non-real-time workload. The first pipeline is configured to resume processing the subsequent primitive on the basis of the first state information stored in the first memory element.