公开(公告)号：US11776885B2

公开(公告)日：2023-10-03

申请号：US17397842

申请日：2021-08-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin Ho ,  Chih-Cheng Lee

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49822

Abstract: A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.

公开(公告)号：US09373601B2

公开(公告)日：2016-06-21

申请号：US14700060

申请日：2015-04-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Cheng Lee ,  Yuan Chang Su ,  Cheng-Lin Ho ,  Chung-Ming Wu ,  You-Lung Yen

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/768 ,  H01L21/683 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76801 ,  H01L21/76877 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/11334 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81801 ,  H01L2924/014 ,  H01L2924/00014

Abstract: The present disclosure relates to a semiconductor substrate, a semiconductor package structure, and methods for making the same. A method includes providing a substrate and a carrier layer. The substrate includes a first patterned metal layer, a second patterned metal layer spaced from the first patterned metal layer, and a dielectric layer disposed between the first patterned metal layer and the second patterned metal layer. The dielectric layer covers the second patterned metal layer. The dielectric layer defines first openings exposing the second patterned metal layer, and further defines a via opening extending from the first patterned metal layer to the second patterned metal layer. A conductive material is disposed in the via and electrically connects the first patterned metal layer to the second patterned metal layer. The carrier layer defines second openings exposing the second patterned metal layer.

Abstract translation: 本公开涉及半导体衬底，半导体封装结构及其制造方法。 一种方法包括提供衬底和载体层。 衬底包括第一图案化金属层，与第一图案化金属层间隔开的第二图案化金属层，以及设置在第一图案化金属层和第二图案化金属层之间的介电层。 电介质层覆盖第二图案化金属层。 电介质层限定暴露第二图案化金属层的第一开口，并且还限定从第一图案化金属层延伸到第二图案化金属层的通孔。 导电材料设置在通孔中并将第一图案化金属层电连接到第二图案化金属层。 载体层限定暴露第二图案化金属层的第二开口。

公开(公告)号：US11756904B2

公开(公告)日：2023-09-12

申请号：US16895989

申请日：2020-06-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yuanhao Yu ,  Cheng-Lin Ho ,  Yu-Lin Shih ,  Shih-Chun Li

IPC: H01L23/66 ,  H01Q1/22

CPC classification number: H01L23/66 ,  H01Q1/2283 ,  H01L2223/6616 ,  H01L2223/6677

Abstract: A semiconductor device package includes a substrate, a reflector, a radiator and a first director. The reflector is disposed on a surface of the substrate. The radiator is disposed over the reflector. The first director is disposed over the radiator. The reflector, the radiator and the first director have different elevations with respect to the surface of the substrate. The radiator and the first director define an antenna.

公开(公告)号：US11201386B2

公开(公告)日：2021-12-14

申请号：US16670487

申请日：2019-10-31

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin Ho ,  Chih-Cheng Lee ,  Chun Chen Chen ,  Yuanhao Yu

IPC: H01L23/495 ,  H01L21/786 ,  H01Q1/22 ,  H01L23/28 ,  H01L21/768 ,  H01L23/66

Abstract: A semiconductor device package and a method for manufacturing the same are provided. The semiconductor device package includes a circuit layer and an antenna module. The circuit layer has a first surface, a second surface opposite to the first surface and a lateral surface. The lateral surface extends between the first surface and the second surface. The circuit layer has an interconnection structure. The antenna module has an antenna pattern layer and is disposed on the first surface of the circuit layer. The lateral surface of the circuit layer is substantially coplanar with a lateral surface of the antenna module.

公开(公告)号：US11024555B2

公开(公告)日：2021-06-01

申请号：US16878475

申请日：2020-05-19

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin Ho ,  Chih-Cheng Lee

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373

Abstract: The present disclosure provides a semiconductor substrate, including a first patterned conductive layer, a dielectric structure on the first patterned conductive layer, wherein the dielectric structure having a side surface, a second patterned conductive layer on the dielectric structure and extending on the side surface, and a third patterned conductive layer on the second patterned conductive layer and extending on the side surface. The present disclosure provides a semiconductor package including the semiconductor substrate. A method for manufacturing the semiconductor substrate and the semiconductor package is also provided.

公开(公告)号：US09984898B2

公开(公告)日：2018-05-29

申请号：US15630847

申请日：2017-06-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li Chuan Tsai ,  Chih-Cheng Lee ,  Cheng-Lin Ho

IPC: H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L21/4857 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/498 ,  H01L24/16

Abstract: A substrate includes a dielectric layer having a first surface and a second surface opposite to the first surface, a first circuit layer and at least one second conductive element. The first circuit layer is disposed adjacent to the first surface of the dielectric layer, and includes at least one trace and at least one first conductive element connected to the trace. The first conductive element does not extend through the dielectric layer. The second conductive element extends through the dielectric layer. An area of an upper surface of the second conductive element is substantially equal to an area of an upper surface of the first conductive element.

公开(公告)号：US11101186B2

公开(公告)日：2021-08-24

申请号：US16297451

申请日：2019-03-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin Ho ,  Chih-Cheng Lee

IPC: H01L27/32 ,  H01L23/31 ,  H01L23/498 ,  H01L21/66 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: A substrate structure includes a wiring structure and a supporter. The wiring structure includes a first dielectric structure, a first circuit layer, a second dielectric structure and a second circuit layer. The first circuit layer is disposed on the first dielectric structure. The second dielectric structure covers the first dielectric structure and the first circuit layer. A pad portion of the first circuit layer is exposed from the first dielectric structure, and the second circuit layer protrudes from the second dielectric structure. The supporter is disposed adjacent to the first dielectric structure of the wiring structure, and defines at least one through hole corresponding to the exposed pad portion of the first circuit layer.

公开(公告)号：US11088061B2

公开(公告)日：2021-08-10

申请号：US16814729

申请日：2020-03-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin Ho ,  Chih-Cheng Lee

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48

Abstract: A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.

公开(公告)号：US11004779B2

公开(公告)日：2021-05-11

申请号：US15893180

申请日：2018-02-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Po-Shu Peng ,  Cheng-Lin Ho ,  Chih-Cheng Lee

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A substrate includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer and comprising an interconnection structure, and an interconnection element. The interconnection element extends from the first surface of the first dielectric layer to the second surface of the first dielectric layer and is surrounded by the interconnection structure.

公开(公告)号：US10886208B2

公开(公告)日：2021-01-05

申请号：US16264602

申请日：2019-01-31

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin Ho ,  Chih-Cheng Lee ,  Chun Chen Chen ,  Chen Yuang Chen

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H05K1/18 ,  H05K3/34 ,  H01L21/48

Abstract: A semiconductor device package includes a carrier, an electronic component, a connection element and an encapsulant. The electronic component is disposed on a surface of the carrier. The connection element is disposed on the surface and adjacent to an edge of the carrier. The encapsulant is disposed on the surface of the carrier. A portion of the connection element is exposed from an upper surface and an edge of the encapsulant.