公开(公告)号：US10985085B2

公开(公告)日：2021-04-20

申请号：US16413467

申请日：2019-05-15

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ian Hu ,  Chih-Pin Hung ,  Meng-Kai Shih

IPC: H01L23/427 ,  H01L25/065 ,  H01L23/367 ,  F28D15/04

Abstract: A thermal conductive device includes a first conductive plate, a second conductive plate, a plurality of wicks and a fluid. The first conductive plate has a first portion adjacent to edges of the first conductive plate and a second portion far away from the edges. The second conductive plate has a first portion adjacent to edges of the first conductive plate and a second portion far away from the edges. The first portion and the second portion of the first conductive plate are respectively connected to the first portion and the second portion of the second conductive plate to define a chamber. The plurality of wicks are disposed within the chamber. The fluid is disposed within the chamber.

公开(公告)号：US10658257B1

公开(公告)日：2020-05-19

申请号：US16178241

申请日：2018-11-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Dao-Long Chen ,  Chih-Pin Hung ,  Ming-Hung Chen

IPC: H01L23/29 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package structure includes a semiconductor die, at least one wiring structure, an encapsulant and a plurality of conductive elements. The semiconductor die has an active surface. The at least one wiring structure is electrically connected to the active surface of the semiconductor die. The encapsulant surrounds the semiconductor die. The encapsulant is formed from an encapsulating material, and a Young's Modulus of the encapsulant is from 0.001 GPa to 1 GPa. The conductive elements are embedded in the encapsulant, and are electrically connected to the at least one wiring structure.

公开(公告)号：US10553527B2

公开(公告)日：2020-02-04

申请号：US15702700

申请日：2017-09-12

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Dao-Long Chen ,  Chih-Pin Hung

IPC: H01L23/498 ,  H01L23/29 ,  H01L23/00

Abstract: A substrate including a dielectric layer and a patterned conductive layer adjacent to the dielectric layer is provided. The patterned conductive layer comprises a first conductive pad, the first conductive pad comprises a first portion having a first concave sidewall. The substrate further includes a protection layer disposed on the patterned conductive layer, and the protection layer covers the first portion of the first conductive pad.

公开(公告)号：US10276382B2

公开(公告)日：2019-04-30

申请号：US15615665

申请日：2017-06-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： John Richard Hunt ,  William T. Chen ,  Chih-Pin Hung ,  Chen-Chao Wang

IPC: H01L21/00 ,  H01L21/108 ,  H01L21/768 ,  H01L23/04 ,  H01L23/48 ,  H01L23/485 ,  H01L23/528 ,  H01L23/00 ,  H01L25/065 ,  H01L27/108 ,  H01L23/16 ,  H01L21/56 ,  H01L21/683 ,  H01L23/538 ,  H01L23/31

Abstract: A semiconductor device package includes an electronic device and a redistribution stack. The redistribution stack includes a dielectric layer disposed over an active surface of the electronic device and defining an opening exposing at least a portion of a contact pad of the electronic device. The redistribution stack also includes a redistribution layer disposed over the dielectric layer and including a trace. A first portion of the trace extends over the dielectric layer along a longitudinal direction adjacent to the opening, and a second portion of the trace is disposed in the opening and extends between the first portion of the trace and the exposed portion of the contact pad. The second portion of the trace has a maximum width along a transverse direction orthogonal to the longitudinal direction, and the maximum width of the second portion of the trace is no greater than about 3 times of a width of the first portion of the trace.

公开(公告)号：US10181448B2

公开(公告)日：2019-01-15

申请号：US15076831

申请日：2016-03-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Pin Hung ,  Dao-Long Chen ,  Ying-Ta Chiu ,  Ping-Feng Yang

IPC: H01L23/00

Abstract: A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent to the surface of the semiconductor element and connected to the trace, and a pillar disposed on the bonding pad. The pillar includes a first end wall, a second end wall opposite the first end wall, a first side wall, and a second side wall opposite the first side wall. The first side wall and the second side wall connect the first end wall to the second end wall. One or both of the first side wall and the second side wall incline inwardly from the first end wall to the second end wall. The pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall.

公开(公告)号：US09917071B1

公开(公告)日：2018-03-13

申请号：US15371889

申请日：2016-12-07

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ying-Ta Chiu ,  Yong-Da Chiu ,  Dao-Long Chen ,  Chih-Cheng Lee ,  Chih-Pin Hung

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L24/83 ,  H01L23/498 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/13017 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/16147 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/32147 ,  H01L2224/81385 ,  H01L2224/81898 ,  H01L2224/83139 ,  H01L2224/83895 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/3511 ,  H01L2224/81

Abstract: A semiconductor package includes: a first substrate including a first interconnection structure extending from a surface of the first substrate, the first interconnection structure including grains of a first size, a second substrate including: a second interconnection structure comprising grains of a second size, and a third interconnection structure disposed between the first interconnection structure and the second interconnection structure, the third interconnection structure including grains of a third size, a first sidewall inclined at a first angle to a reference plane and a second sidewall inclined at a second angle to the reference plane, wherein the first angle is different from the second angle, the first sidewall is disposed between the first substrate and the second sidewall, and the third size is smaller than both the first size and the second size.

公开(公告)号：US09917043B2

公开(公告)日：2018-03-13

申请号：US15479074

申请日：2017-04-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien Lin Chang Chien ,  Chin-Li Kao ,  Chang Chi Lee ,  Chih-Pin Hung

IPC: H01L23/498 ,  H01L21/48 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/562 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06586

Abstract: In one or more embodiments, a semiconductor package includes a redistribution layer, a conductive pad, a dielectric layer, a silicon layer, and a conductive contact. The redistribution layer includes a first surface and a second surface opposite to the first surface. The conductive pad is on the first surface of the redistribution layer. The dielectric layer is disposed on the first surface of the redistribution layer to cover a first portion of the conductive pad and to expose a second portion of the conductive pad. The silicon layer is disposed on the dielectric layer, the silicon layer having a recess to expose the second portion of the conductive pad. The conductive contact is disposed over the silicon layer and extends into the recess of the silicon layer.

公开(公告)号：US11894317B2

公开(公告)日：2024-02-06

申请号：US17003883

申请日：2020-08-26

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Po-Hsien Ke ,  Teck-Chong Lee ,  Chih-Pin Hung

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L23/562 ,  H01L21/563 ,  H01L23/3135 ,  H01L25/0652 ,  H01L25/50

Abstract: A package structure and a manufacturing method are provided. The package structure includes a wiring structure, a first electronic device, a second electronic device, a first underfill, a second underfill and a stiff bonding material. The first electronic device and the second electronic device are disposed on the wiring structure, and are electrically connected to each other through the wiring structure. The first underfill is disposed in a first space between the first electronic device and the wiring structure. The second underfill is disposed in a second space between the second electronic device and the wiring structure. The stiff bonding material is disposed in a central gap between the first electronic device and the second electronic device. The stiff bonding material is different from the first underfill and the second underfill.

公开(公告)号：US11139222B2

公开(公告)日：2021-10-05

申请号：US16566502

申请日：2019-09-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Jung-Che Tsai ,  Ian Hu ,  Chih-Pin Hung

IPC: H01L23/427 ,  H01L23/36 ,  H01L23/00

Abstract: An electronic device includes a main substrate, a semiconductor package structure and at least one heat pipe. The semiconductor package structure is electrically connected to the main substrate, and includes a die mounting portion, a semiconductor die and a cover structure. The semiconductor die is disposed on the die mounting portion. The cover structure covers the semiconductor die. The heat pipe contacts the cover structure for dissipating a heat generated by the semiconductor die.

公开(公告)号：US11081420B2

公开(公告)日：2021-08-03

申请号：US16508210

申请日：2019-07-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsin-En Chen ,  Ian Hu ,  Chih-Pin Hung

IPC: H01L23/34 ,  H01L23/367 ,  H01L23/427

Abstract: A semiconductor package structure includes a package substrate, at least one semiconductor die, a heat dissipating device, at least one electronic device and a heat transmitting structure. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is electrically connected to the first surface of the package substrate. The heat dissipating device is thermally connected to the first surface of the package substrate. The electronic device is electrically connected to the second surface of the package substrate. The electronic device has a first surface and a second surface opposite to the first surface, and the first surface of the electronic device faces the second surface of the package substrate. The heat transmitting structure is disposed adjacent to the second surface of the package substrate, and thermally connected to the electronic device and the heat dissipating device.