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Patent Agency Ranking
公开(公告)号：US20120226949A1
公开(公告)日：2012-09-06
申请号：US13038430
申请日：2011-03-02
Applicant: Alexandre Pierre Palus , Karl Friedrich Greb
Inventor： Alexandre Pierre Palus , Karl Friedrich Greb
IPC: G06F11/07
CPC classification number: G06F11/10 , G06F11/0745 , G06F11/0751 , G06F11/0793 , G06F11/1443
Abstract: An embodiment of the invention provides a method for managing errors on a bus. Information read from a source is encoded. The encoded information is transmitted on a channel that is part of the bus. The encoded information is evaluated. When no errors are detected, the decoded information is provided to a target. When the decoded information has an error or errors that can not be corrected, the source is asked to present the information to the bus again. When an error or errors can be corrected, the corrected information is sent to the target.
Abstract translation: 本发明的实施例提供了一种用于管理总线上的错误的方法。 从源中读取的信息被编码。 编码信息在作为总线一部分的信道上传输。 对编码信息进行评估。 当没有检测到错误时，解码的信息被提供给目标。 当解码信息有错误或无法纠正的错误时，请求来源将信息再次呈现给总线。 当可以纠正错误或错误时，将更正的信息发送到目标。
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2.发明申请Locking/Unlocking CPUs to Operate in Safety Mode or Performance Mode Without Rebooting 有权锁定/解锁CPU在安全模式或性能模式下运行，无需重新启动公开(公告)号：US20120185628A1
公开(公告)日：2012-07-19
申请号：US13008082
申请日：2011-01-18
Applicant: Alexandre Pierre Palus
Inventor： Alexandre Pierre Palus
CPC classification number: G06F9/44505 , G06F9/38 , G06F9/3861 , G06F11/1641 , G06F11/1658 , G06F11/1675 , G06F13/24 , G06F2201/845
Abstract: An embodiment of the invention provides a method for changing a multi-processor system from a performance mode to a safety mode while the system continues to run software. When an external event or exception occurs, context is switched from the performance mode to the safety mode. After context is switched, at least one pair of CPUs is synchronized to operate in the safety mode. In addition, a multi-processor system may be switched form the safety mode to the performance mode while the software continues to operate.
Abstract translation: 本发明的实施例提供了一种在系统继续运行软件时将多处理器系统从性能模式改变为安全模式的方法。 当外部事件或异常发生时，上下文从性能模式切换到安全模式。 在上下文切换之后，至少一对CPU被同步以在安全模式下操作。 此外，当软件继续运行时，多处理器系统可以从安全模式切换到性能模式。
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3.发明授权Locking/unlocking CPUs to operate in safety mode or performance mode without rebooting 有权锁定/解锁CPU以安全模式或性能模式运行，无需重新启动公开(公告)号：US09405637B2
公开(公告)日：2016-08-02
申请号：US13008082
申请日：2011-01-18
Applicant: Alexandre Pierre Palus
Inventor： Alexandre Pierre Palus
CPC classification number: G06F9/44505 , G06F9/38 , G06F9/3861 , G06F11/1641 , G06F11/1658 , G06F11/1675 , G06F13/24 , G06F2201/845
Abstract: An embodiment of the invention provides a method for changing a multi-processor system from a performance mode to a safety mode while the system continues to run software. When an external event or exception occurs, context is switched from the performance mode to the safety mode. After context is switched, at least one pair of CPUs is synchronized to operate in the safety mode. In addition, a multi-processor system may be switched form the safety mode to the performance mode while the software continues to operate.
Abstract translation: 本发明的实施例提供了一种在系统继续运行软件时将多处理器系统从性能模式改变为安全模式的方法。 当外部事件或异常发生时，上下文从性能模式切换到安全模式。 在上下文切换之后，至少一对CPU被同步以在安全模式下操作。 此外，当软件继续运行时，多处理器系统可以从安全模式切换到性能模式。
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4.发明授权公开(公告)号：US08972821B2
公开(公告)日：2015-03-03
申请号：US13330877
申请日：2011-12-20
Applicant: Yanyang Xiao , Alexandre Pierre Palus , Karl Friedrich Greb , Kevin Patrick Lavery , Paul Krause
Inventor： Yanyang Xiao , Alexandre Pierre Palus , Karl Friedrich Greb , Kevin Patrick Lavery , Paul Krause
CPC classification number: G06F11/0763 , G06F9/3004 , G06F9/30076 , G06F11/1008 , G06F11/1016 , G06F11/1048 , G06F11/1068 , G06F11/1641 , G06F11/1654 , G06F11/28 , G06F13/4013 , G06K9/00986 , G11C29/00 , G11C29/14 , G11C29/48 , G11C29/52 , G11C2029/0411 , H03M13/13 , H03M13/27
Abstract: An electronic circuit includes a microcontroller processor (410), a peripheral (420) coupled with the processor, an endian circuit (470) coupled with the processor and the peripheral to selectively provide different endianess modes of operation, and a detection circuit (140) to detect a failure to select a given endianess, whereby inadvertent switch of endianess due to faults is avoided. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.
Abstract translation: 电子电路包括微处理器（410），与处理器耦合的外围设备（420），与处理器和外围设备耦合的端电路（470），以选择性地提供不同的端对端操作模式;以及检测电路（140） 检测到无法选择给定的字节码，从而避免了由于故障导致的无意识切换。 还公开了其它电路，装置，系统，操作方法和制造方法。
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5.发明申请DUAL ENDIANESS AND OTHER CONFIGURATION SAFETY IN LOCK STEP DUAL-CORE SYSTEM, AND OTHER CIRCUITS, PROCESSES AND SYSTEMS 有权锁定步骤双核系统及其他电路，处理和系统中的双重任务和其他配置安全公开(公告)号：US20120173924A1
公开(公告)日：2012-07-05
申请号：US13330877
申请日：2011-12-20
Applicant: Yanyang Xiao , Alexandre Pierre Palus , Karl Friedrich Greb , Kevin Patrick Lavery , Paul Krause
Inventor： Yanyang Xiao , Alexandre Pierre Palus , Karl Friedrich Greb , Kevin Patrick Lavery , Paul Krause
IPC: G06F11/14
CPC classification number: G06F11/0763 , G06F9/3004 , G06F9/30076 , G06F11/1008 , G06F11/1016 , G06F11/1048 , G06F11/1068 , G06F11/1641 , G06F11/1654 , G06F11/28 , G06F13/4013 , G06K9/00986 , G11C29/00 , G11C29/14 , G11C29/48 , G11C29/52 , G11C2029/0411 , H03M13/13 , H03M13/27
Abstract: An electronic circuit includes a microcontroller processor (410), a peripheral (420) coupled with the processor, an endian circuit (470) coupled with the processor and the peripheral to selectively provide different endianess modes of operation, and a detection circuit (140) to detect a failure to select a given endianess, whereby inadvertent switch of endianess due to faults is avoided. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.
Abstract translation: 电子电路包括微处理器（410），与处理器耦合的外围设备（420），与处理器和外围设备耦合的端电路（470），以选择性地提供不同的端对端操作模式;以及检测电路（140） 检测到无法选择给定的字节码，从而避免了由于故障导致的无意识切换。 还公开了其它电路，装置，系统，操作方法和制造方法。
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