公开(公告)号：US20180109262A1

公开(公告)日：2018-04-19

申请号：US15666293

申请日：2017-08-01

Applicant: Altera Corporation

Inventor： Andy Lee ,  Herman Schmit

IPC: H03K19/177

CPC classification number: H03K19/17724 ,  H03K19/00315 ,  H03K19/17764

Abstract: An integrated circuit formed using a semiconductor substrate may include a logic circuit and a switch circuit, whereby the logic circuit operates at a first power supply voltage and the switch circuit operates at a second power supply voltage that is greater than the first power supply voltage. The logic circuit may be formed within a first triple well structure within the semiconductor substrate and is supplied with a first bias voltage. The switch circuit may be formed within a second triple well structure that is electrically isolated from the first triple well structure within the semiconductor substrate and is supplied with a second bias voltage. The switch circuit may receive a control signal that controls the first bias voltage and the second power supply voltage to turn off a transistor in the logic circuit during a programming operation of the integrated circuit.

公开(公告)号：US09755647B1

公开(公告)日：2017-09-05

申请号：US15294588

申请日：2016-10-14

Applicant: Altera Corporation

Inventor： Andy Lee ,  Herman Schmit

IPC: G06F7/38 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17724 ,  H03K19/00315 ,  H03K19/17764

Abstract: An integrated circuit formed using a semiconductor substrate may include a logic circuit and a switch circuit, whereby the logic circuit operates at a first power supply voltage and the switch circuit operates at a second power supply voltage that is greater than the first power supply voltage. The logic circuit may be formed within a first triple well structure within the semiconductor substrate and is supplied with a first bias voltage. The switch circuit may be formed within a second triple well structure that is electrically isolated from the first triple well structure within the semiconductor substrate and is supplied with a second bias voltage. The switch circuit may receive a control signal that controls the first bias voltage and the second power supply voltage to turn off a transistor in the logic circuit during a programming operation of the integrated circuit.

公开(公告)号：US09397095B1

公开(公告)日：2016-07-19

申请号：US14222630

申请日：2014-03-22

Applicant: Altera Corporation

Inventor： Ning Cheng ,  Andy Lee

IPC: H01L29/06 ,  H01L27/088 ,  H01L27/118 ,  H01L27/02

CPC classification number: H01L27/0886 ,  H01L27/0207 ,  H01L27/11803

Abstract: A FinFET comprises a substrate, an array of substantially parallel fins formed on the substrate and extending in a first direction, and an array of gates on the fins. First gates extend across the same fins of a first plurality of the fins in a second direction transverse to the first. Second gates extend across the same fins of a second plurality of fins in the second direction; the second gates having a length that is larger than that of the first gates. Third gates extend across the same fins of a third plurality of fins in the second direction; the third plurality of fins being located between the first and second pluralities. The third gates provide a transition between the first gates and the second gates in which a first portion of the third gates are dummies and a second portion are active devices such as pass gates.

Abstract translation: FinFET包括衬底，形成在衬底上并沿第一方向延伸的基本上平行的翅片的阵列，以及翅片上的阵列阵列。 第一门在与第一门横向的第二方向上延伸穿过第一组多个翅片的相同翅片。 第二门在第二方向上延伸穿过第二多个翅片的相同翅片; 第二栅极的长度大于第一栅极的长度。 第三门在第二方向上延伸穿过第三多个翅片的相同翅片; 所述第三多个翅片位于所述第一和第二多个之间。 第三栅极提供第一栅极和第二栅极之间的转变，其中第三栅极的第一部分是虚拟物，第二部分是诸如栅极的有源器件。

公开(公告)号：US09099531B1

公开(公告)日：2015-08-04

申请号：US14332266

申请日：2014-07-15

Applicant: Altera Corporation

Inventor： Ning Cheng ,  Andy Lee ,  Fangyun Richter

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L21/033 ,  H01L21/308

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A plurality of elongated, substantially parallel mandrels are formed on a first work surface, the mandrels being spaced apart a distance in the range between the resolution limit and twice the resolution limit. Spacers are formed on the work surface extending from sidewalls of the mandrels. First portions of the work surface are exposed through gaps in the spacers near the midpoint between a majority of adjacent mandrels; but at least one pair of adjacent mandrels is close enough together that the spacers extend continuously between the adjacent mandrels. The mandrels are then removed, thereby exposing second portions of the work surface. The exposed first and second portions are etched down to a second work surface; and the exposed portions of the second work surface are etched to form trenches in that surface. A wire routing is formed by filling the trenches with a metal such as copper.

Abstract translation: 在第一工作表面上形成多个细长的基本平行的心轴，所述心轴在分辨率极限和分辨率极限的两倍之间的范围内间隔开一段距离。 间隔件形成在从心轴的侧壁延伸的工作表面上。 工作表面的第一部分通过间隔物中的间隙附近暴露在大多数相邻心轴之间的中点附近; 但是至少一对相邻的心轴足够接近，使得间隔件在相邻的心轴之间连续地延伸。 然后去除心轴，从而暴露工作表面的第二部分。 暴露的第一和第二部分被蚀刻到第二工作表面; 并且蚀刻第二工作表面的暴露部分以在该表面中形成沟槽。 通过用诸如铜的金属填充沟槽来形成布线。

公开(公告)号：US09667314B1

公开(公告)日：2017-05-30

申请号：US14970367

申请日：2015-12-15

Applicant: Altera Corporation

Inventor： Shuxian Chen ,  Andy Lee ,  Jeffrey Watt ,  Mark Chan

IPC: H04B3/36 ,  H04B3/18

CPC classification number: H04B3/36 ,  H04B3/18

Abstract: An integrated circuit includes a buffer circuit, a receiving circuit, and a programmable repeater circuit. The programmable repeater circuit includes a routing input and an enable input. The programmable repeater circuit buffers an input signal received at the routing input from the buffer circuit through a first conductor to generate an output signal that is provided to an input of the receiving circuit through a second conductor only in response to an enable signal at the enable input enabling the programmable repeater circuit.