公开(公告)号：US09606176B2

公开(公告)日：2017-03-28

申请号：US14627856

申请日：2015-02-20

Applicant: Altera Corporation

Inventor： Marc Miller ,  Steven Teig ,  Jason Redgrave ,  Brad Hutchings ,  Danny Thom

IPC: G01R31/28 ,  G01R31/3177

CPC classification number: G01R31/3177 ,  G06F11/221 ,  G11C2029/0409

Abstract: Some embodiments provide an integrated circuit (“IC”) with a primary circuit structure. The primary circuit structure is for performing multiple operations that implement a user design. The primary circuit structure includes multiple circuits. The IC also includes a secondary monitoring structure for monitoring multiple operations. The secondary monitoring structure includes a network communicatively coupled to multiple circuits of the primary circuit structure. The secondary monitoring circuit structure is for analyzing the monitored operations and reporting on the analysis to a circuit outside of the IC.

公开(公告)号：US09489175B2

公开(公告)日：2016-11-08

申请号：US14311359

申请日：2014-06-23

Applicant: Altera Corporation

Inventor： Herman Schmit ,  Jason Redgrave

IPC: H03K19/173 ,  G06F7/506

CPC classification number: G06F7/506 ,  G06F2207/3868 ,  H03K19/173

Abstract: Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two.

Abstract translation: 一些实施例提供了包括若干可配置逻辑电路的可配置IC，其中逻辑电路包括若干组相关联的可配置逻辑电路。 对于每组几组相关联的可配置逻辑电路，可重新配置的IC还包括一个执行多达N个进位操作的进位电路，其中N大于2。

公开(公告)号：US09385725B2

公开(公告)日：2016-07-05

申请号：US14664755

申请日：2015-03-20

Applicant: Altera Corporation

Inventor： Brad Hutchings ,  Jason Redgrave ,  Teju Khubchandani ,  Herman Schmit ,  Steven Teig

IPC: G06F7/38 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/1731 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/17756 ,  H03K19/17764

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. In some embodiments, the configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. In some of these embodiments, the configuration network is a pipelined network. Also, the IC of some embodiments includes a configuration controller for retrieving configuration data from outside of the IC, formulating configuration data sets, and routing the configuration data sets to the second set of configurable circuits over the configuration network.

公开(公告)号：US09461650B2

公开(公告)日：2016-10-04

申请号：US14665673

申请日：2015-03-23

Applicant: Altera Corporation

Inventor： Jason Redgrave

IPC: G06F7/38 ,  H03K19/177

CPC classification number: H03K19/1776 ,  H03K19/17744

Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions. The configurable IC also includes a set of configurable routing circuits for routing signals to and from the configurable circuits. During several operational cycles of the configurable IC, a set of data registers are defined by the configurable routing circuits. These data registers may be used wherever a flip-flop can be used.

公开(公告)号：US20160087635A1

公开(公告)日：2016-03-24

申请号：US14672097

申请日：2015-03-28

Applicant: Altera Corporation

Inventor： Andre Rohe ,  Steven Teig ,  Herman Schmit ,  Jason Redgrave ,  Andrew Caldwell

IPC: H03K19/177 ,  G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/5077 ,  H03K19/173 ,  H03K19/17736 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/17776

Abstract: Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time. Some embodiments provide a method of designing a reconfigurable IC that has several reconfigurable circuits, each having several configurations and operating in several reconfiguration cycles. The method identifies a signal path through the IC that does not meet a timing constraint. The signal path includes several circuits, one of which is a particular reconfigurable circuit. The method then maintains a configuration of the particular reconfigurable circuit constant over at least two contiguous reconfiguration cycles in order to reduce signal delay through the signal path and thereby satisfy the timing constraint.

Abstract translation: 一些实施例提供可重构集成电路（“IC”）。 该IC具有几个可重新配置电路，每个具有几个配置周期的配置。 可重新配置的电路包括几个延时可重构电路。 在IC的操作期间，每个特定的时间延长的可重新配置电路在至少两个连续周期内保持其配置中的至少一个，以便允许信号传播通过包含特定延时电路的信号路径， 在期望的时间内。 一些实施例提供了一种设计可重配置IC的方法，该可重配置IC具有若干可重构电路，每个可重新配置电路具有若干配置并在几个重新配置周期中操作。 该方法识别通过IC的不符合定时约束的信号路径。 信号路径包括几个电路，其中之一是特定的可重新配置电路。 该方法然后在至少两个连续的重新配置周期上保持特定可重新配置电路的配置不变，以减少通过信号路径的信号延迟，从而满足定时约束。

公开(公告)号：US20160028399A1

公开(公告)日：2016-01-28

申请号：US14664755

申请日：2015-03-20

Applicant: Altera Corporation

Inventor： Brad Hutchings ,  Jason Redgrave ,  Teju Khubchandani ,  Herman Schmit ,  Steven Teig

IPC: H03K19/173 ,  H03K19/177

CPC classification number: H03K19/1731 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/17756 ,  H03K19/17764

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. In some embodiments, the configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. In some of these embodiments, the configuration network is a pipelined network. Also, the IC of some embodiments includes a configuration controller for retrieving configuration data from outside of the IC, formulating configuration data sets, and routing the configuration data sets to the second set of configurable circuits over the configuration network.

Abstract translation: 本发明的一些实施例提供了一种可配置集成电路（IC），其具有用于可配置地执行不同操作的多个可配置电路。 在IC的操作期间，每个特定可配置电路执行由针对特定可配置电路的特定配置数据集指定的特定操作。 当IC操作并且第一组可配置电路执行第一组操作时，从IC的外部加载配置数据，用于配置第二组可配置电路。 在一些实施例中，可配置IC包括用于从IC外部快速加载IC中的配置数据的配置网络。 在这些实施例中的一些实施例中，配置网络是流水线网络。 此外，一些实施例的IC包括用于从IC外部检索配置数据的配置控制器，配置数据组，以及通过配置网络将配置数据集路由到第二组可配置电路。

公开(公告)号：US20150326227A1

公开(公告)日：2015-11-12

申请号：US14665673

申请日：2015-03-23

Applicant: Altera Corporation

Inventor： Jason Redgrave

IPC: H03K19/177

CPC classification number: H03K19/1776 ,  H03K19/17744

Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions. The configurable IC also includes a set of configurable routing circuits for routing signals to and from the configurable circuits. During several operational cycles of the configurable IC, a set of data registers are defined by the configurable routing circuits. These data registers may be used wherever a flip-flop can be used.

Abstract translation: 本发明的一些实施例提供了可配置的集成电路（“IC”）。 可配置IC包括用于可配置地执行一组功能的一组可配置逻辑电路。 可配置IC还包括一组可配置路由电路，用于将信号路由到可配置电路和从可配置电路路由信号。 在可配置IC的几个操作周期期间，一组数据寄存器由可配置的路由电路定义。 这些数据寄存器可以用于可以使用触发器的地方。

公开(公告)号：US09494967B2

公开(公告)日：2016-11-15

申请号：US14279159

申请日：2014-05-15

Applicant: Altera Corporation

Inventor： Brad Hutchings ,  Jason Redgrave ,  Dai Huang ,  Steven Teig

IPC: H03K19/0175 ,  G06F1/04 ,  G06M3/00 ,  H03K19/177

CPC classification number: G06F1/04 ,  G06M3/00 ,  H03K19/017581 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/1776 ,  H03K19/17764

Abstract: Some embodiments provide an integrated circuit (“IC”). The IC includes multiple configurable circuits that configurably perform operations of a user design based on configuration data. The IC also includes a configurable trigger circuit that receives a set of configuration data that specifies an operational event. The configurable trigger circuit also determines whether the operational event has occurred during implementation of the user design of the IC. Additionally, the operational trigger event outputs a trigger signal upon determining that the operational trigger event has occurred.

Abstract translation: 一些实施例提供集成电路（“IC”）。 IC包括可配置地基于配置数据执行用户设计操作的多个可配置电路。 IC还包括可配置触发电路，其接收指定操作事件的一组配置数据。 可配置触发电路还确定在实施IC的用户设计期间是否发生了操作事件。 此外，当确定操作触发事件已经发生时，操作触发事件输出触发信号。

公开(公告)号：US09276572B2

公开(公告)日：2016-03-01

申请号：US14599738

申请日：2015-01-19

Applicant: Altera Corporation

Inventor： Martin Voogel ,  Jason Redgrave ,  Trevis Chandler

IPC: H03K19/00 ,  H03K3/037 ,  H03K19/177 ,  G06F15/78 ,  G11C7/10

CPC classification number: H03K19/0008 ,  G06F15/7867 ,  G11C7/1045 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H03K3/0372 ,  H03K19/17732 ,  H03K19/17748 ,  H03K19/17752 ,  H03K19/17768 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.