公开(公告)号：US20180041201A1

公开(公告)日：2018-02-08

申请号：US15230150

申请日：2016-08-05

Applicant: Altera Corporation

Inventor： Lai Guan Tang ,  Kang Syn Ting

IPC: H03K7/08 ,  H02M1/14 ,  H02M3/00

CPC classification number: H03K7/08 ,  H02M1/14 ,  H02M3/00

Abstract: An integrated circuit includes a control circuit, a first-in first-out circuit, and a serializer circuit. The control circuit generates parallel pulse-width modulation data in first parallel pulse-width modulation signals. The first-in first-out circuit stores the parallel pulse-width modulation data indicated by the first parallel pulse-width modulation signals. The first-in first-out circuit outputs the stored parallel pulse-width modulation data in second parallel pulse-width modulation signals. The serializer circuit converts the parallel pulse-width modulation data indicated by the second parallel pulse-width modulation signals to serial pulse-width modulation data in a serial pulse-width modulation signal.

公开(公告)号：US10177753B2

公开(公告)日：2019-01-08

申请号：US15230150

申请日：2016-08-05

Applicant: Altera Corporation

Inventor： Lai Guan Tang ,  Kang Syn Ting

IPC: H03K3/00 ,  H03K7/08 ,  H02M1/14 ,  H02M3/00

Abstract: An integrated circuit includes a control circuit, a first-in first-out circuit, and a serializer circuit. The control circuit generates parallel pulse-width modulation data in first parallel pulse-width modulation signals. The first-in first-out circuit stores the parallel pulse-width modulation data indicated by the first parallel pulse-width modulation signals. The first-in first-out circuit outputs the stored parallel pulse-width modulation data in second parallel pulse-width modulation signals. The serializer circuit converts the parallel pulse-width modulation data indicated by the second parallel pulse-width modulation signals to serial pulse-width modulation data in a serial pulse-width modulation signal.

公开(公告)号：US10346331B2

公开(公告)日：2019-07-09

申请号：US15193654

申请日：2016-06-27

Applicant: ALTERA CORPORATION

Inventor： Si Xing Saw ,  Seng Kuan Yeow ,  Kang Syn Ting

IPC: G06F13/36 ,  H04L7/00 ,  G06F13/362 ,  G06F13/22

Abstract: One embodiment relates to a data detection and event capture circuit. Data comparator logic receives a monitored data word from a parallel data bus and generates a plurality of pattern detected signals. Any pattern detection logic receives the plurality of pattern detected signals and generates a plurality of any pattern detected signals. Sequence detection logic receives the plurality of pattern detected signals and generates a plurality of sequence detected signals. Another embodiment relates to a method of data detection and event capture. Another embodiment relates to an integrated circuit having a first data detection and event capture circuit in a receiver circuit and a second data detection and event capture circuit in a transmitter circuit. Other embodiments and features are also disclosed.