公开(公告)号：US20150206965A1

公开(公告)日：2015-07-23

申请号：US14222629

申请日：2014-03-22

Applicant: Altera Corporation

Inventor： Ning Cheng ,  Peter J. McElheny

IPC: H01L29/78 ,  H01L21/8238

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L29/1054

Abstract: A FinFET is described having first, second, and third pluralities of fins with gate structures and source and drain regions formed on the fins so that PMOS transistors are formed on the first plurality of fins, NMOS transistors are formed on the second plurality and PMOS transistors are formed on the third plurality. In one embodiment, the first and second pluralities of fins are made of strained silicon; and the third plurality of fins is made of a material such as germanium or silicon germanium that has a higher hole mobility than strained silicon. In a second embodiment, the first plurality of fins is made of silicon, the second plurality of strained silicon, germanium or a III-V compound; and the third plurality is made of germanium or silicon germanium.

Abstract translation: 描述了具有第一，第二和第三多个翅片的FinFET，其栅极结构和源极和漏极区域形成在鳍片上，使得PMOS晶体管形成在第一多个鳍片上，NMOS晶体管形成在第二多个鳍片上，PMOS晶体管 形成在第三多个。 在一个实施例中，第一和第二多个翅片由应变硅制成; 并且第三多个翅片由诸如锗或硅锗的材料制成，其具有比应变硅更高的空穴迁移率。 在第二实施例中，第一多个翅片由硅制成，第二多个应变硅，锗或III-V化合物; 并且第三多个由锗或硅锗制成。

公开(公告)号：US09984734B2

公开(公告)日：2018-05-29

申请号：US15471325

申请日：2017-03-28

Applicant: Altera Corporation

Inventor： Andy L. Lee ,  Shankar Sinha ,  Ning Cheng

IPC: G11C7/00 ,  G11C7/22 ,  G11C5/14 ,  G11C7/20

CPC classification number: G11C7/22 ,  G11C5/14 ,  G11C7/20 ,  G11C11/413 ,  G11C11/419 ,  G11C2207/002

Abstract: Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors.

公开(公告)号：US09299396B1

公开(公告)日：2016-03-29

申请号：US14331470

申请日：2014-07-15

Applicant: Altera Corporation

Inventor： Andy L. Lee ,  Shankar Sinha ,  Ning Cheng

IPC: G11C7/00 ,  G11C5/14

CPC classification number: G11C7/22 ,  G11C5/14 ,  G11C7/20 ,  G11C11/413 ,  G11C11/419 ,  G11C2207/002

Abstract: Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors.

Abstract translation: 集成电路可以包括用于重新配置存储器阵列的一部分的部分重新配置（PR）电路。 在一些应用中，可以在用户模式期间执行部分重新配置。 在部分重新配置期间，可以施加诸如改变电源电压的写入辅助技术以帮助增加写入裕度，但是这样做可能潜在地影响在用户模式期间由存储器阵列控制的工作中通过门的性能。 在一种合适的布置中，可以在包括p沟道存取晶体管的存储器单元上实现接地电源电压写入辅助技术，并且其用于控制​​n沟道传输晶体管。 在另一种合适的布置中，正电源电压写入辅助技术可以在包括n沟道存取晶体管的存储器单元上实现，并且用于控制p沟道传输晶体管。

公开(公告)号：US20170200484A1

公开(公告)日：2017-07-13

申请号：US15471325

申请日：2017-03-28

Applicant: Altera Corporation

Inventor： Andy L. Lee ,  Shankar Sinha ,  Ning Cheng

IPC: G11C7/22 ,  G11C7/20 ,  G11C5/14

CPC classification number: G11C7/22 ,  G11C5/14 ,  G11C7/20 ,  G11C11/413 ,  G11C11/419 ,  G11C2207/002

Abstract: Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors.

公开(公告)号：US09397095B1

公开(公告)日：2016-07-19

申请号：US14222630

申请日：2014-03-22

Applicant: Altera Corporation

Inventor： Ning Cheng ,  Andy Lee

IPC: H01L29/06 ,  H01L27/088 ,  H01L27/118 ,  H01L27/02

CPC classification number: H01L27/0886 ,  H01L27/0207 ,  H01L27/11803

Abstract: A FinFET comprises a substrate, an array of substantially parallel fins formed on the substrate and extending in a first direction, and an array of gates on the fins. First gates extend across the same fins of a first plurality of the fins in a second direction transverse to the first. Second gates extend across the same fins of a second plurality of fins in the second direction; the second gates having a length that is larger than that of the first gates. Third gates extend across the same fins of a third plurality of fins in the second direction; the third plurality of fins being located between the first and second pluralities. The third gates provide a transition between the first gates and the second gates in which a first portion of the third gates are dummies and a second portion are active devices such as pass gates.

Abstract translation: FinFET包括衬底，形成在衬底上并沿第一方向延伸的基本上平行的翅片的阵列，以及翅片上的阵列阵列。 第一门在与第一门横向的第二方向上延伸穿过第一组多个翅片的相同翅片。 第二门在第二方向上延伸穿过第二多个翅片的相同翅片; 第二栅极的长度大于第一栅极的长度。 第三门在第二方向上延伸穿过第三多个翅片的相同翅片; 所述第三多个翅片位于所述第一和第二多个之间。 第三栅极提供第一栅极和第二栅极之间的转变，其中第三栅极的第一部分是虚拟物，第二部分是诸如栅极的有源器件。

公开(公告)号：US09099531B1

公开(公告)日：2015-08-04

申请号：US14332266

申请日：2014-07-15

Applicant: Altera Corporation

Inventor： Ning Cheng ,  Andy Lee ,  Fangyun Richter

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L21/033 ,  H01L21/308

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A plurality of elongated, substantially parallel mandrels are formed on a first work surface, the mandrels being spaced apart a distance in the range between the resolution limit and twice the resolution limit. Spacers are formed on the work surface extending from sidewalls of the mandrels. First portions of the work surface are exposed through gaps in the spacers near the midpoint between a majority of adjacent mandrels; but at least one pair of adjacent mandrels is close enough together that the spacers extend continuously between the adjacent mandrels. The mandrels are then removed, thereby exposing second portions of the work surface. The exposed first and second portions are etched down to a second work surface; and the exposed portions of the second work surface are etched to form trenches in that surface. A wire routing is formed by filling the trenches with a metal such as copper.

Abstract translation: 在第一工作表面上形成多个细长的基本平行的心轴，所述心轴在分辨率极限和分辨率极限的两倍之间的范围内间隔开一段距离。 间隔件形成在从心轴的侧壁延伸的工作表面上。 工作表面的第一部分通过间隔物中的间隙附近暴露在大多数相邻心轴之间的中点附近; 但是至少一对相邻的心轴足够接近，使得间隔件在相邻的心轴之间连续地延伸。 然后去除心轴，从而暴露工作表面的第二部分。 暴露的第一和第二部分被蚀刻到第二工作表面; 并且蚀刻第二工作表面的暴露部分以在该表面中形成沟槽。 通过用诸如铜的金属填充沟槽来形成布线。

公开(公告)号：US10037992B1

公开(公告)日：2018-07-31

申请号：US14579831

申请日：2014-12-22

Applicant: Altera Corporation

Inventor： Zhiyuan Wu ,  Ning Cheng ,  Christopher J. Pass

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/033

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0653

Abstract: A transistor device is provided. The transistor device includes a group of fins formed in a substrate, where the group of fins comprises at least one enabled fin and at least one disabled fin. Each of the fins has first and second fin portions. The first fin portion encompasses a drain region and the second fin portion of the fins encompasses a source region. These two regions are separated by a channel region. A gate structure is formed over the fins and channel region and in between the first fin portion and the second fin portion of the fins. The transistor device further includes a conductive structure. The conductive structure shorts the first fin portion of the at least one disabled fin to the second fin portion of the at least one disabled fin.

公开(公告)号：US09892922B1

公开(公告)日：2018-02-13

申请号：US13936066

申请日：2013-07-05

Applicant: Altera Corporation

Inventor： Ning Cheng ,  Peter Smeys

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/28 ,  H01L27/092

CPC classification number: H01L21/28008 ,  H01L27/092

Abstract: A method of fabricating an integrated circuit includes forming a plurality of polysilicon gate electrode structures over a plurality of fin-shaped channel structures. A portion of the plurality of polysilicon gate electrode structures may then be removed to expose a surface region of a fin-shaped channel structure in the plurality of fin-shaped channel structures. The remaining portion of the polysilicon gate electrode structures may form a plurality of polysilicon transistors. A layer of high-k dielectric material is deposited on the exposed surface region of the fin-shaped channel structure. A metal layer may be deposited over the high-k dielectric material to form at least one high-k metal gate transistor over the fin-shaped channel structure.

公开(公告)号：US09607671B1

公开(公告)日：2017-03-28

申请号：US15061440

申请日：2016-03-04

Applicant: Altera Corporation

Inventor： Andy L. Lee ,  Shankar Sinha ,  Ning Cheng

IPC: G11C7/00 ,  G11C7/20 ,  G11C5/14

CPC classification number: G11C7/22 ,  G11C5/14 ,  G11C7/20 ,  G11C11/413 ,  G11C11/419 ,  G11C2207/002

Abstract: Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors.

公开(公告)号：US09166045B1

公开(公告)日：2015-10-20

申请号：US14473953

申请日：2014-08-29

Applicant: Altera Corporation

Inventor： Che Ta Hsu ,  Fangyun Richter ,  Ning Cheng ,  Jeffrey Xiaoqi Tung

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L27/092

CPC classification number: H01L29/7833 ,  H01L21/02115 ,  H01L21/02126 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/8232 ,  H01L21/8238 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66583

Abstract: In an illustrative embodiment, holes are formed in an insulating layer where the gates of NMOS and PMOS transistors are to be formed; and a hard mask spacer layer is formed on the exposed surfaces. Next, spacers are formed on the sidewalls of the holes by anisotropically etching the spacer layer to remove the portion of the spacer layer exposed at the bottom of each hole while leaving some of the spacer layer formed on the sidewalls of the holes. A high-k dielectric layer is then formed between the spacers; and a metal layer is formed on the high-k dielectric layer. Bulk metal layer is then formed on the metal layer. Chemical mechanical polishing is performed to remove the bulk gate metal down to the insulating layer, thereby isolating individual NMOS and PMOS gate structures.

Abstract translation: 在说明性实施例中，在要形成NMOS和PMOS晶体管的栅极的绝缘层中形成空穴; 并且在暴露的表面上形成硬掩模间隔层。 接下来，通过各向异性蚀刻间隔层以去除在每个孔的底部暴露的间隔层的部分，同时留下形成在孔的侧壁上的一些间隔层，在孔的侧壁上形成间隔物。 然后在间隔物之间​​形成高k电介质层; 并且在高k电介质层上形成金属层。 然后在金属层上形成块状金属层。 执行化学机械抛光以将体栅极金属去除到绝缘层，从而隔离各个NMOS和PMOS栅极结构。