公开(公告)号：US20170200484A1

公开(公告)日：2017-07-13

申请号：US15471325

申请日：2017-03-28

Applicant: Altera Corporation

Inventor： Andy L. Lee ,  Shankar Sinha ,  Ning Cheng

IPC: G11C7/22 ,  G11C7/20 ,  G11C5/14

CPC classification number: G11C7/22 ,  G11C5/14 ,  G11C7/20 ,  G11C11/413 ,  G11C11/419 ,  G11C2207/002

Abstract: Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors.

公开(公告)号：US09496268B2

公开(公告)日：2016-11-15

申请号：US14268183

申请日：2014-05-02

Applicant: Altera Corporation

Inventor： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

IPC: G11C11/412 ,  H01L27/11 ,  G11C7/10 ,  G11C5/06 ,  H01L21/8234

CPC classification number: H01L27/1104 ,  G11C5/06 ,  G11C7/1051 ,  G11C11/412 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/82345 ,  H01L29/1045 ,  H01L29/4983 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66659

Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

公开(公告)号：US08995177B1

公开(公告)日：2015-03-31

申请号：US14142004

申请日：2013-12-27

Applicant: Altera Corporation

Inventor： Shankar Sinha ,  Shih-Lin S. Lee ,  Peter J. McElheny

IPC: G11C11/00 ,  H01L21/70 ,  H01L27/105 ,  H01L27/11

CPC classification number: H01L27/1052 ,  G11C11/412 ,  H01L27/1104

Abstract: Integrated circuits with memory elements are provided. A memory element may include a storage circuit coupled to data lines through access transistors. Access transistors may be used to read data from and write data into the storage circuit. An access transistor may have asymmetric source-drain resistances. The access transistor may have a first source-drain that is coupled to a data line and a second source-drain that is coupled to the storage circuit. The second source-drain may have a contact resistance that is greater than the contact resistance associated with the first source-drain. Access transistors with asymmetric source-drain resistances may have a first drive strength when passing a low signal and a second drive strength when passing a high signal to the storage circuit. The second drive strength may be less than the first drive strength. Access transistors with asymmetric drive strengths may be used to improve memory read/write performance.

Abstract translation: 提供具有存储元件的集成电路。 存储元件可以包括通过存取晶体管耦合到数据线的存储电路。 存取晶体管可用于从存储电路读取数据并将数据写入存储电路。 存取晶体管可以具有不对称的源极 - 漏极电阻。 存取晶体管可以具有耦合到数据线的第一源极 - 漏极和耦合到存储电路的第二源极 - 漏极。 第二源极 - 漏极可以具有大于与第一源极 - 漏极相关联的接触电阻的接触电阻。 具有不对称源极 - 漏极电阻的存取晶体管在通过高信号到存储电路时通过低信号和第二驱动强度时可具有第一驱动强度。 第二驱动强度可能小于第一驱动强度。 具有非对称驱动强度的存取晶体管可用于提高存储器读/写性能。

公开(公告)号：US09984734B2

公开(公告)日：2018-05-29

申请号：US15471325

申请日：2017-03-28

Applicant: Altera Corporation

Inventor： Andy L. Lee ,  Shankar Sinha ,  Ning Cheng

IPC: G11C7/00 ,  G11C7/22 ,  G11C5/14 ,  G11C7/20

CPC classification number: G11C7/22 ,  G11C5/14 ,  G11C7/20 ,  G11C11/413 ,  G11C11/419 ,  G11C2207/002

Abstract: Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors.

公开(公告)号：US09299396B1

公开(公告)日：2016-03-29

申请号：US14331470

申请日：2014-07-15

Applicant: Altera Corporation

Inventor： Andy L. Lee ,  Shankar Sinha ,  Ning Cheng

IPC: G11C7/00 ,  G11C5/14

CPC classification number: G11C7/22 ,  G11C5/14 ,  G11C7/20 ,  G11C11/413 ,  G11C11/419 ,  G11C2207/002

Abstract: Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors.

Abstract translation: 集成电路可以包括用于重新配置存储器阵列的一部分的部分重新配置（PR）电路。 在一些应用中，可以在用户模式期间执行部分重新配置。 在部分重新配置期间，可以施加诸如改变电源电压的写入辅助技术以帮助增加写入裕度，但是这样做可能潜在地影响在用户模式期间由存储器阵列控制的工作中通过门的性能。 在一种合适的布置中，可以在包括p沟道存取晶体管的存储器单元上实现接地电源电压写入辅助技术，并且其用于控制​​n沟道传输晶体管。 在另一种合适的布置中，正电源电压写入辅助技术可以在包括n沟道存取晶体管的存储器单元上实现，并且用于控制p沟道传输晶体管。

公开(公告)号：US09276083B2

公开(公告)日：2016-03-01

申请号：US13715442

申请日：2012-12-14

Applicant: Altera Corporation

Inventor： Shankar Sinha ,  Brian Wong ,  Shih-Lin Lee ,  Wei Zhang ,  Abhishek Bankey Behari Sharma

IPC: H01L29/66 ,  G11C11/412 ,  H01L27/02 ,  H01L27/11

CPC classification number: H01L29/66477 ,  G11C11/412 ,  G11C11/4125 ,  H01L27/0207 ,  H01L27/1104

Abstract: Integrated circuits with memory cells are provided. A memory cell may include first and second cross-coupled inverting circuits configured to store a single data bit. The first inverting circuit may have an output serving as a first data storage node for the memory cell, whereas the second inverting circuit may have an output serving as a second data storage node for the memory cell. Access transistors may be coupled between the first and second data storage nodes and corresponding data lines. Each of the first and second inverting circuit may have a pull-down transistor and at least two pull-up transistors stacked in series. The pull-down transistors may have body terminals that are reverse biased to help reduce leakage current through the first and second inverting circuits. The memory cell may be formed using a narrower two-gate configuration or a wider four-gate configuration.

Abstract translation: 提供具有存储单元的集成电路。 存储器单元可以包括被配置为存储单个数据位的第一和第二交叉耦合反相电路。 第一反相电路可以具有用作存储单元的第一数据存储节点的输出，而第二反相电路可以具有用作存储单元的第二数据存储节点的输出。 存取晶体管可以耦合在第一和第二数据存储节点和对应的数据线之间。 第一和第二反相电路中的每一个可以具有串联堆叠的下拉晶体管和至少两个上拉晶体管。 下拉晶体管可以具有反向偏置的主体端子，以帮助减少通过第一和第二反相电路的泄漏电流。 可以使用较窄的双栅极配置或较宽的四栅极配置来形成存储单元。

公开(公告)号：US08750026B1

公开(公告)日：2014-06-10

申请号：US13923276

申请日：2013-06-20

Applicant: Altera Corporation

Inventor： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

IPC: G11C11/412 ,  G11C7/10 ,  G11C8/16

CPC classification number: G11C11/412

Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

Abstract translation: 不对称晶体管可以通过在晶体管的一个源极 - 漏极端子上而不是另一个产生凹穴注入来形成。 也可以使用具有不同功函数的第一和第二栅极导体的双栅结构来形成非对称晶体管。 可以通过堆叠相同通道类型的两个晶体管串联形成堆叠晶体管。 两个晶体管中的每一个的源极 - 漏极端子之一连接到公共节点。 两个晶体管的栅极也连接在一起。 两个晶体管可以具有不同的阈值电压。 位于堆叠晶体管中较高的晶体管的阈值电压可以具有比堆叠晶体管中的另一个晶体管更低的阈值电压。 堆叠的晶体管可用于减少诸如存储器单元的电路中的漏电流。 不对称晶体管也可用于存储器单元中以减少泄漏。

公开(公告)号：US09607671B1

公开(公告)日：2017-03-28

申请号：US15061440

申请日：2016-03-04

Applicant: Altera Corporation

Inventor： Andy L. Lee ,  Shankar Sinha ,  Ning Cheng

IPC: G11C7/00 ,  G11C7/20 ,  G11C5/14

CPC classification number: G11C7/22 ,  G11C5/14 ,  G11C7/20 ,  G11C11/413 ,  G11C11/419 ,  G11C2207/002

Abstract: Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors.

公开(公告)号：US09576617B1

公开(公告)日：2017-02-21

申请号：US14297063

申请日：2014-06-05

Applicant: Altera Corporation

Inventor： Shih-Lin S. Lee ,  Peter J. McElheny ,  Preminder Singh ,  Shankar Sinha

IPC: G11C8/16 ,  G11C7/00 ,  G06F12/14

CPC classification number: G11C7/00 ,  G06F12/1425 ,  G11C8/16 ,  G11C2029/0411

Abstract: Integrated circuits with multiport memory elements may be provided. A multiport memory element may include a latching circuit, a first set of address transistors, and a second set of address transistors. The latching circuit may include cross-coupled inverters, each of which includes a pull-up transistor and a pull-down transistor. The first set of address transistors may couple the latching circuit to a write port, whereas the second set of address transistors may couple the latching circuit to a read port. The pull-down transistors and the second set of address transistors may have body bias terminals that are controlled by a control signal. During data loading operations, the control signal may be temporarily elevated to weaken the pull-down transistors and the second set of address transistors to improve the write margin of the multiport memory element.

Abstract translation: 可以提供具有多端口存储器元件的集成电路。 多端口存储元件可以包括锁存电路，第一组地址晶体管和第二组地址晶体管。 锁存电路可以包括交叉耦合的反相器，每个反相器包括上拉晶体管和下拉晶体管。 第一组地址晶体管可以将锁存电路耦合到写入端口，而第二组地址晶体管可以将锁存电路耦合到读取端口。 下拉晶体管和第二组地址晶体管可以具有由控制信号控制的体偏置端子。 在数据加载操作期间，控制信号可以临时升高以削弱下拉晶体管和第二组地址晶体管，以改善多端口存储器元件的写入裕度。

公开(公告)号：US20160232952A9

公开(公告)日：2016-08-11

申请号：US14268183

申请日：2014-05-02

Applicant: Altera Corporation

Inventor： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

IPC: G11C7/10 ,  G11C5/06

CPC classification number: H01L27/1104 ,  G11C5/06 ,  G11C7/1051 ,  G11C11/412 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/82345 ,  H01L29/1045 ,  H01L29/4983 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66659

Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.