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公开(公告)号：US20180294817A1
公开(公告)日：2018-10-11
申请号：US15957766
申请日：2018-04-19
Applicant: Analog Devices, Inc.
Inventor： Christopher Mayer , David J. McLaurin , Christopher W. Angell , Sudhir Desai , Steven R. Bal
Abstract: Apparatus and methods for phase synchronization of phase-locked loops (PLLs) are provided. In certain configurations, an RF communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit that synchronizes a phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on timing of a reference clock signal. Additionally, the phase synchronization circuit includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit further includes a phase adjustment control circuit that provides a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL.
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Patent Agency Ranking
公开(公告)号：US09979408B2
公开(公告)日：2018-05-22
申请号：US15147408
申请日：2016-05-05
Applicant: ANALOG DEVICES, INC.
Inventor： Christopher Mayer , David J. McLaurin , Christopher W. Angell , Sudhir Desai , Steven R. Bal
CPC classification number: H03L7/1976 , H03L7/087 , H03L7/0891 , H03L7/091 , H03L7/093 , H03L7/23 , H03L7/235 , H04B7/0413 , H04L7/0331
Abstract: Apparatus and methods for phase synchronization of phase-locked loops (PLLs) are provided. In certain configurations, an RF communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit that synchronizes a phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on timing of a reference clock signal. Additionally, the phase synchronization circuit includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit further includes a phase adjustment control circuit that provides a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL.
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公开(公告)号：US20250036842A1
公开(公告)日：2025-01-30
申请号：US18781029
申请日：2024-07-23
Applicant: Analog Devices, Inc.
Inventor： Christopher Mayer , Sudhir Desai , Arash Azizimazreah
IPC: G06F30/347 , G06F13/40 , H04L49/101
Abstract: Apparatus and methods for facilitating data movement among circuit blocks are disclosed. In certain embodiments, dataflow gaskets with circular buffers are deployed in any number or arrangement to achieve efficient on-chip data movement among different circuit blocks of the die. Each dataflow gasket can be attached to a corresponding circuit block using tightly coupled memories to provide low latency and fast access to incoming and outgoing data streams. Furthermore, memory allocation and buffer management can be handled by the internal logic in the dataflow gasket to reduce or eliminate software development efforts. For example, the dataflow gasket can use circular buffers to allow the circuit block to access the dataflow gasket's memories without needing to understand the internal memory addressing of the dataflow gasket.
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公开(公告)号：US20170324419A1
公开(公告)日：2017-11-09
申请号：US15147408
申请日：2016-05-05
Applicant: ANALOG DEVICES, INC.
Inventor： Christopher Mayer , David J. McLaurin , Christopher W. Angell , Sudhir Desai , Steven R. Bal
CPC classification number: H03L7/1976 , H03L7/087 , H03L7/0891 , H03L7/091 , H03L7/093 , H03L7/23 , H03L7/235 , H04B7/0413 , H04L7/0331
Abstract: Apparatus and methods for phase synchronization of phase-locked loops (PLLs) are provided. In certain configurations, an RF communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit that synchronizes a phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on timing of a reference clock signal. Additionally, the phase synchronization circuit includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit further includes a phase adjustment control circuit that provides a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL.
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公开(公告)号：US20250036587A1
公开(公告)日：2025-01-30
申请号：US18780879
申请日：2024-07-23
Applicant: Analog Devices, Inc.
Inventor： Christopher Mayer , Sudhir Desai , Arash Azizimazreah
IPC: G06F13/36
Abstract: Apparatus and methods for facilitating data movement among circuit blocks are disclosed. In certain embodiments, an integrated circuit (IC) includes a network of dataflow gaskets including a first dataflow gasket coupled to a first circuit block and a second dataflow gasket coupled to a second circuit block. The first circuit block can write to the second circuit block by programming output stream registers of the first dataflow gasket for an outgoing write stream that includes a header identifying the second dataflow gasket. The header can be provided by the first dataflow gasket to the second dataflow gasket over the network, and in response to the header reaching the second dataflow gasket, the second dataflow gasket can program the input stream registers of the second dataflow gasket for an incoming read stream.
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公开(公告)号：US10659065B2
公开(公告)日：2020-05-19
申请号：US15957766
申请日：2018-04-19
Applicant: Analog Devices, Inc.
Inventor： Christopher Mayer , David J. McLaurin , Christopher W. Angell , Sudhir Desai , Steven R. Bal
Abstract: Apparatus and methods for phase synchronization of phase-locked loops (PLLs) are provided. In certain configurations, an RF communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit that synchronizes a phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on timing of a reference clock signal. Additionally, the phase synchronization circuit includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit further includes a phase adjustment control circuit that provides a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL.
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