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公开(公告)号：US20190114433A1
公开(公告)日：2019-04-18
申请号：US16206092
申请日：2018-11-30
Applicant: Apple Inc.
Inventor： Joshua P. de Cesare , Timothy R. Paaske , Xeno S. Kovah , Nikolaj Schlej , Jeffrey R. Wilcox , Hardik K. Doshi , Kevin H. Alderfer , Corey T. Kallenberg
IPC: G06F21/57 , G06F21/62 , G06F9/4401 , G06F21/79
Abstract: A method and apparatus for protecting boot variables is disclosed. A computer system includes a main processor and an auxiliary processor. The auxiliary processor is associated with a non-volatile memory that stores variables associated with boot code that is also stored thereon. The main processor may send a request to the auxiliary processor to alter one of the variables stored in the non-volatile memory. Responsive to receiving the request, the auxiliary processor may execute a security policy to determine if the main processor meets the criteria for altering the variable. If the auxiliary processor determines that the main processor meets the criteria, it may grant permission to alter the variable.
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公开(公告)号：US20190102558A1
公开(公告)日：2019-04-04
申请号：US16205838
申请日：2018-11-30
Applicant: Apple Inc.
Inventor： Joshua P. de Cesare , Timothy R. Paaske , Xeno S. Kovah , Nikolaj Schlej , Jeffrey R. Wilcox , Ezekiel T. Runyon , Hardik K. Doshi , Kevin H. Alderfer , Corey T. Kallenberg
IPC: G06F21/57 , G06F9/4401
Abstract: A method and apparatus for performing a secure boot of a computer system is disclosed. A computer system according to the disclosure includes an auxiliary processor and a main processor. The boot process includes initially booting the auxiliary processor. The auxiliary processor is associated with a non-volatile memory storing boot code for the main processor. The auxiliary processor may perform a verification of the boot code. Subsequent to verifying the boot code, the main processor may be released from a reset state. Once the main processor is no longer in the reset state, the boot code may be provided thereto. Thereafter, the boot procedure may continue with the main processor executing the boot code.
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公开(公告)号：US11307921B2
公开(公告)日：2022-04-19
申请号：US17114388
申请日：2020-12-07
Applicant: Apple Inc.
Inventor： Christopher J. Noe , Joshua H. Berlin , Joseph J. Castro , Hardik K. Doshi , Joel N. Kerr , Kerry J. Kopp , Michael J. Smith
Abstract: One embodiment provides for a data processing system comprising multiple independent processors to execute multiple operating system environments of the data processing system, the multiple operating system environments to enable operation of multiple regions of a computing device associated with the data processing system. The multiple operating system environments are interconnected via a transport agnostic communication link. In response to detection of a fatal error in one or more of the multiple operating system environments, the multiple operating system environments coordinate performance of multiple separate error handling operations within the multiple operating system environments to generate a combined error log. The combined error log includes operational states of the multiple operating system environments.
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公开(公告)号：US10223128B2
公开(公告)日：2019-03-05
申请号：US15285202
申请日：2016-10-04
Applicant: Apple Inc.
Inventor： Hardik K. Doshi
IPC: G06F9/00 , G06F15/177 , G06F9/4401 , G06F1/3287 , G06F1/3203 , G06F1/3293
Abstract: A computing device may comprise a first processor and a secondary processor. The first processor may initiate a power management process transitioning the first processor from a first state to a second state and, upon reaching a predetermined step in the power management process, notify the secondary processor of the power management process. The secondary processor may initiate, in response to the notifying, a parallel power management process transitioning the secondary processor from an equivalent first state to an equivalent second state.
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公开(公告)号：US20180349608A1
公开(公告)日：2018-12-06
申请号：US15721365
申请日：2017-09-29
Applicant: Apple Inc.
Inventor： Joshua P. de Cesare , Timothy R. Paaske , Xeno S. Kovah , Nikolaj Schlej , Jeffrey R. Wilcox , Ezekiel T. Runyon , Hardik K. Doshi , Kevin H. Alderfer , Corey T. Kallenberg
CPC classification number: G06F21/575
Abstract: A method and apparatus for performing a secure boot of a computer system is disclosed. A computer system according to the disclosure includes an auxiliary processor and a main processor. The boot process includes initially booting the auxiliary processor. The auxiliary processor includes a non-volatile memory storing boot code for the main processor. The auxiliary processor may perform a verification of the boot code. Subsequent to verifying the boot code, the main processor may be released from a reset state. Once the main processor is no longer in the reset state, the boot code may be provided thereto. Thereafter, the boot procedure may continue with the main processor executing the boot code.
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Patent Agency Ranking
公开(公告)号：US11263326B2
公开(公告)日：2022-03-01
申请号：US15721365
申请日：2017-09-29
Applicant: Apple Inc.
Inventor： Joshua P. de Cesare , Timothy R. Paaske , Xeno S. Kovah , Nikolaj Schlej , Jeffrey R. Wilcox , Ezekiel T. Runyon , Hardik K. Doshi , Kevin H. Alderfer , Corey T. Kallenberg
IPC: G06F9/4401 , G06F21/57 , G06F21/44
Abstract: A method and apparatus for performing a secure boot of a computer system is disclosed. A computer system according to the disclosure includes an auxiliary processor and a main processor. The boot process includes initially booting the auxiliary processor. The auxiliary processor includes a non-volatile memory storing boot code for the main processor. The auxiliary processor may perform a verification of the boot code. Subsequent to verifying the boot code, the main processor may be released from a reset state. Once the main processor is no longer in the reset state, the boot code may be provided thereto. Thereafter, the boot procedure may continue with the main processor executing the boot code.
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公开(公告)号：US20210117265A1
公开(公告)日：2021-04-22
申请号：US17114388
申请日：2020-12-07
Applicant: Apple Inc.
Inventor： Christopher J. Noe , Joshua H. Berlin , Joseph J. Castro , Hardik K. Doshi , Joel N. Kerr , Kerry J. Kopp , Michael J. Smith
Abstract: One embodiment provides for a data processing system comprising multiple independent processors to execute multiple operating system environments of the data processing system, the multiple operating system environments to enable operation of multiple regions of a computing device associated with the data processing system. The multiple operating system environments are interconnected via a transport agnostic communication link. In response to detection of a fatal error in one or more of the multiple operating system environments, the multiple operating system environments coordinate performance of multiple separate error handling operations within the multiple operating system environments to generate a combined error log. The combined error log includes operational states of the multiple operating system environments.
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公开(公告)号：US10908919B2
公开(公告)日：2021-02-02
申请号：US16290566
申请日：2019-03-01
Applicant: Apple Inc.
Inventor： Hardik K. Doshi
IPC: G06F9/00 , G06F15/177 , G06F9/4401 , G06F1/3287 , G06F1/3203 , G06F1/3293
Abstract: A computing device may comprise a first processor and a secondary processor. The first processor may initiate a power management process transitioning the first processor from a first state to a second state and, upon reaching a predetermined step in the power management process, notify the secondary processor of the power management process. The secondary processor may initiate, in response to the notifying, a parallel power management process transitioning the secondary processor from an equivalent first state to an equivalent second state.
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公开(公告)号：US20190179695A1
公开(公告)日：2019-06-13
申请号：US16147330
申请日：2018-09-28
Applicant: Apple Inc.
Inventor： Christopher J. Noe , Joshua H. Berlin , Joseph J. Castro , Hardik K. Doshi , Joel N. Kerr , Kerry J. Kopp , Michael J. Smith
IPC: G06F11/07
Abstract: One embodiment provides for a data processing system comprising multiple independent processors to execute multiple operating system environments of the data processing system, the multiple operating system environments to enable operation of multiple regions of a computing device associated with the data processing system. The multiple operating system environments are interconnected via a transport agnostic communication link. In response to detection of a fatal error in one or more of the multiple operating system environments, the multiple operating system environments coordinate performance of multiple separate error handling operations within the multiple operating system environments to generate a combined error log. The combined error log includes operational states of the multiple operating system environments.
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公开(公告)号：US10860412B2
公开(公告)日：2020-12-08
申请号：US16147330
申请日：2018-09-28
Applicant: Apple Inc.
Inventor： Christopher J. Noe , Joshua H. Berlin , Joseph J. Castro , Hardik K. Doshi , Joel N. Kerr , Kerry J. Kopp , Michael J. Smith
IPC: G06F11/07
Abstract: One embodiment provides for a data processing system comprising multiple independent processors to execute multiple operating system environments of the data processing system, the multiple operating system environments to enable operation of multiple regions of a computing device associated with the data processing system. The multiple operating system environments are interconnected via a transport agnostic communication link. In response to detection of a fatal error in one or more of the multiple operating system environments, the multiple operating system environments coordinate performance of multiple separate error handling operations within the multiple operating system environments to generate a combined error log. The combined error log includes operational states of the multiple operating system environments.
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