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公开(公告)号：US12265844B2
公开(公告)日：2025-04-01
申请号：US17468312
申请日：2021-09-07
Applicant: Apple Inc.
Inventor： Benjamin Bowman , Fergus W. MacGarry , Kutty Banerjee , Pratik Chandresh Shah
IPC: G06F9/48
Abstract: Disclosed techniques relate to circuitry configured to aggregate and report usage information in a distributed processor (e.g., a GPU). In some embodiments, graphics processor circuitry that includes at least first and second portions that are respectively configured to execute sets of graphics work. First utilization circuitry may track execution time for sets of graphics work on the first portion of the graphics processor circuitry and second utilization circuitry may track execution time for sets of graphics work on the second portion of the graphics processor circuitry. Command queue circuitry may store multiple different command queues. Control circuitry may access the first and second utilization circuitry and aggregate utilization data on a per-command-queue basis, where for a given command queue, the aggregated utilization data indicates respective utilization of the first and second portions of the graphics processor circuitry. The control circuitry may provide the aggregated per-command-queue utilization data in software-accessible registers.
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公开(公告)号：US11741017B2
公开(公告)日：2023-08-29
申请号：US17654726
申请日：2022-03-14
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Pratik Chandresh Shah , Tatsuya Iwamoto , David E. Roberts
IPC: G06F12/00 , G06F12/1027
CPC classification number: G06F12/1027 , G06F2212/683
Abstract: One disclosed embodiment includes a method for memory management. The method includes receiving a first request to clear one or more entries of a translation lookaside buffer (TLB), receiving a second request to clear one or more entries of the TLB, bundling the first request with the second request, determining that a processor associated with the TLB transitioned to an inactive mode, and dropping the bundled first and second requests based on the determination.
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3.发明授权公开(公告)号：US11275697B2
公开(公告)日：2022-03-15
申请号：US16786231
申请日：2020-02-10
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Pratik Chandresh Shah , Tatsuya Iwamoto , David E. Roberts
IPC: G06F12/1027
Abstract: One disclosed embodiment includes a method for memory management. The method includes receiving a first request to clear one or more entries of a translation lookaside buffer (TLB), receiving a second request to clear one or more entries of the TLB, bundling the first request with the second request, determining that a processor associated with the TLB transitioned to an inactive mode, and dropping the bundled first and second requests based on the determination.
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公开(公告)号：US20230075531A1
公开(公告)日：2023-03-09
申请号：US17468312
申请日：2021-09-07
Applicant: Apple Inc.
Inventor： Benjamin Bowman , Fergus W. MacGarry , Kutty Banerjee , Pratik Chandresh Shah
IPC: G06F9/48
Abstract: Disclosed techniques relate to circuitry configured to aggregate and report usage information in a distributed processor (e.g., a GPU). In some embodiments, graphics processor circuitry that includes at least first and second portions that are respectively configured to execute sets of graphics work. First utilization circuitry may track execution time for sets of graphics work on the first portion of the graphics processor circuitry and second utilization circuitry may track execution time for sets of graphics work on the second portion of the graphics processor circuitry. Command queue circuitry may store multiple different command queues. Control circuitry may access the first and second utilization circuitry and aggregate utilization data on a per-command-queue basis, where for a given command queue, the aggregated utilization data indicates respective utilization of the first and second portions of the graphics processor circuitry. The control circuitry may provide the aggregated per-command-queue utilization data in software-accessible registers.
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公开(公告)号：US20200104180A1
公开(公告)日：2020-04-02
申请号：US16145573
申请日：2018-09-28
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Benjamin Bowman , Terence M. Potter , Tatsuya Iwamoto , Gokhan Avkarogullari
Abstract: In general, embodiments are disclosed for tracking and allocating graphics processor hardware resources. More particularly, a graphics hardware resource allocation system is able to generate a priority list for a plurality of data masters for graphics processor based on a comparison between a current utilizations for the data masters and a target utilizations for the data masters. The graphics hardware resource allocation system designate, based on the priority list, a first data master with a higher priority to submit work to the graphics processor compared to a second data master. The graphics hardware resource allocation system determines a stall counter value for the data master and generates a notification to pause work for the second data master based on the stall counter value.
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Patent Agency Ranking
公开(公告)号：US09747659B2
公开(公告)日：2017-08-29
申请号：US14851629
申请日：2015-09-11
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Eric O. Sunalp , Tatsuya Iwamoto
CPC classification number: G06T1/20 , G06F9/5044 , G06F9/505 , G06F2209/5021 , G06T2200/28
Abstract: Embodiments are directed toward systems and methods for scheduling resources of a graphics processing unit that determine, for a number of applications having commands to be issued to the GPU, a static priority level and a dynamic priority level of each application, work iteratively across static priority levels until a resource budget of the GPU is consumed, and starting with a highest static priority identify the applications in a present static priority level, assign a processing budget of the GPU to each of the applications in the present static priority level according to their dynamic priority levels, and admit to a queue commands from the applications in the present static priority level according to their processing budgets, and release the queue to the GPU.
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公开(公告)号：US12039368B2
公开(公告)日：2024-07-16
申请号：US17468328
申请日：2021-09-07
Applicant: Apple Inc.
Inventor： Benjamin Bowman , Fergus W. MacGarry , Kutty Banerjee , Pratik Chandresh Shah
CPC classification number: G06F9/4881 , G06F9/4831 , G06F9/5011 , G06F9/5038 , G06F9/546 , G06T1/20
Abstract: Disclosed techniques relate to distributing graphics work based on priority. In some embodiments, circuitry implements a plurality of tracking slots for sets of graphics work. A set of graphics processor sub-units may each implement multiple distributed hardware slots. Control circuitry may attempt to assign a first set of graphics work having a first priority to a graphics processor sub-unit that is currently executing graphics work having an equal or higher priority than the first priority, where the first set of graphics work is from a first tracking slot. The control circuitry may, in response to a failure of the attempt, generate a signal to graphics software that indicates the failure, wherein the signal indicates the first tracking slot. Disclosed techniques may reduce or avoid problems relating to higher priority work being scheduled behind lower priority work.
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公开(公告)号：US11436055B2
公开(公告)日：2022-09-06
申请号：US16688487
申请日：2019-11-19
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Michael Imbrogno
Abstract: A first command is fetched for execution on a GPU. Dependency information for the first command, which indicates a number of parent commands that the first command depends on, is determined. The first command is inserted into an execution graph based on the dependency information. The execution graph defines an order of execution for plural commands including the first command. The number of parent commands are configured to be executed on the GPU before executing the first command. A wait count for the first command, which indicates the number of parent commands of the first command, is determined based on the execution graph. The first command is inserted into cache memory in response to determining that the wait count for the first command is zero or that each of the number of parent commands the first command depends on has already been inserted into the cache memory.
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公开(公告)号：US20200379920A1
公开(公告)日：2020-12-03
申请号：US16786231
申请日：2020-02-10
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Pratik Chandresh Shah , Tatsuya Iwamoto , David E. Roberts
IPC: G06F12/1027
Abstract: One disclosed embodiment includes a method for memory management. The method includes receiving a first request to clear one or more entries of a translation lookaside buffer (TLB), receiving a second request to clear one or more entries of the TLB, bundling the first request with the second request, determining that a processor associated with the TLB transitioned to an inactive mode, and dropping the bundled first and second requests based on the determination.
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公开(公告)号：US10795730B2
公开(公告)日：2020-10-06
申请号：US16145573
申请日：2018-09-28
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Benjamin Bowman , Terence M. Potter , Tatsuya Iwamoto , Gokhan Avkarogullari
Abstract: In general, embodiments are disclosed for tracking and allocating graphics processor hardware resources. More particularly, a graphics hardware resource allocation system is able to generate a priority list for a plurality of data masters for graphics processor based on a comparison between a current utilizations for the data masters and a target utilizations for the data masters. The graphics hardware resource allocation system designate, based on the priority list, a first data master with a higher priority to submit work to the graphics processor compared to a second data master. The graphics hardware resource allocation system determines a stall counter value for the data master and generates a notification to pause work for the second data master based on the stall counter value.
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