公开(公告)号：US10661383B2

公开(公告)日：2020-05-26

申请号：US16439553

申请日：2019-06-12

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Jungrae Park ,  Ajay Kumar ,  Brad Eaton

IPC: H01L21/00 ,  B23K26/0622 ,  H01L21/683 ,  H01L21/78 ,  H01L21/67 ,  B23K26/06 ,  B23K26/18 ,  B23K26/402 ,  B23K26/364 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  B23K101/42 ,  B23K103/00

Abstract: Methods of dicing semiconductor wafers are described. In an example, a method of dicing a wafer having a plurality of integrated circuits thereon involves dicing the wafer into a plurality of singulated dies disposed above a dicing tape. The method also involves forming a material layer over and between the plurality of singulated dies above the dicing tape. The method also includes expanding the dicing tape, wherein a plurality of particles is collected on the material layer during the expanding.

公开(公告)号：US20200118880A1

公开(公告)日：2020-04-16

申请号：US16706541

申请日：2019-12-06

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01L21/822 ,  H01L21/3065 ,  B23K26/36 ,  H01L23/544 ,  H01L21/67 ,  H01J37/32 ,  H01L21/78 ,  H01L21/308

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US10566238B2

公开(公告)日：2020-02-18

申请号：US16193886

申请日：2018-11-16

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01L21/00 ,  H01L21/822 ,  H01L21/308 ,  H01L21/67 ,  H01L21/78 ,  H01J37/32 ,  H01L23/544 ,  B23K26/36 ,  H01L21/3065 ,  H01L21/683

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US20190291206A1

公开(公告)日：2019-09-26

申请号：US16439553

申请日：2019-06-12

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Jungrae Park ,  Ajay Kumar ,  Brad Eaton

IPC: B23K26/0622 ,  H01L21/67 ,  B23K26/364 ,  H01L21/683 ,  B23K26/06 ,  H01L21/78 ,  B23K26/402 ,  B23K26/18

Abstract: Methods of dicing semiconductor wafers are described. In an example, a method of dicing a wafer having a plurality of integrated circuits thereon involves dicing the wafer into a plurality of singulated dies disposed above a dicing tape. The method also involves forming a material layer over and between the plurality of singulated dies above the dicing tape. The method also includes expanding the dicing tape, wherein a plurality of particles is collected on the material layer during the expanding.

公开(公告)号：US10363629B2

公开(公告)日：2019-07-30

申请号：US15611015

申请日：2017-06-01

Applicant: APPLIED MATERIALS, INC.

Inventor： Wei-Sheng Lei ,  Jungrae Park ,  Ajay Kumar ,  Brad Eaton

IPC: H01L21/00 ,  B23K26/0622 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/308 ,  H01L21/683 ,  H01L21/78 ,  H01L21/67 ,  B23K26/06 ,  B23K26/18 ,  B23K26/402 ,  B23K26/364 ,  B23K101/42 ,  B23K103/00

Abstract: Methods of dicing semiconductor wafers are described. In an example, a method of dicing a wafer having a plurality of integrated circuits thereon involves dicing the wafer into a plurality of singulated dies disposed above a dicing tape. The method also involves forming a material layer over and between the plurality of singulated dies above the dicing tape. The method also includes expanding the dicing tape, wherein a plurality of particles is collected on the material layer during the expanding.

公开(公告)号：US20190088549A1

公开(公告)日：2019-03-21

申请号：US16193886

申请日：2018-11-16

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01L21/822 ,  H01J37/32 ,  H01L21/67 ,  H01L21/3065 ,  B23K26/36 ,  H01L23/544 ,  H01L21/78 ,  H01L21/308 ,  H01L21/683

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US09754765B2

公开(公告)日：2017-09-05

申请号：US14042490

申请日：2013-09-30

Applicant: Applied Materials, Inc.

Inventor： Banqiu Wu ,  Saravjeet Singh ,  Amitabh Sabharwal ,  Ajay Kumar

IPC: H01J37/32

CPC classification number: H01J37/32082 ,  H01J37/32541 ,  H01J37/32568 ,  H01J37/32577 ,  Y10T156/10

Abstract: An electrode having a first portion and a second portion is formed over a substrate to couple to a bias RF power. The first portion is configured to compensate for an electric field at the second portion to even out a distribution of an etching strength over a workpiece placed over the electrode.

公开(公告)号：US09583375B2

公开(公告)日：2017-02-28

申请号：US14563901

申请日：2014-12-08

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/683 ,  H01L21/78 ,  H01L21/67 ,  H01L23/31 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/56

CPC classification number: H01L21/6836 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/561 ,  H01L21/563 ,  H01L21/67069 ,  H01L21/67115 ,  H01L21/67207 ,  H01L21/78 ,  H01L23/3114 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/014

Abstract: Methods and systems for forming water soluble masks by dry film lamination are described. Also described are methods of wafer dicing, including formation of a water soluble mask by dry film lamination. In one embodiment, a method involves moisturizing an inner area of a water soluble dry film. The method involves stretching the water soluble dry film over a surface of the semiconductor wafer, and attaching the moistened inner area of the stretched film to the surface of the semiconductor wafer. A method of wafer dicing may further involve patterning the water soluble dry film, exposing regions of the semiconductor wafer between the ICs, and etching the semiconductor wafer through gaps in the patterned water soluble dry film.

Abstract translation: 描述了通过干膜层压形成水溶性掩模的方法和系统。 还描述了晶片切割的方法，包括通过干膜层压形成水溶性掩模。 在一个实施方案中，一种方法涉及保湿水溶性干膜的内部区域。 该方法包括在半导体晶片的表面上拉伸水溶性干膜，并将拉伸膜的湿润内部区域附着到半导体晶片的表面。 晶片切割的方法还可以包括图案化水溶性干膜，暴露半导体晶片在IC之间的区域，以及通过图案化的水溶性干膜中的间隙蚀刻半导体晶片。

公开(公告)号：US09425062B2

公开(公告)日：2016-08-23

申请号：US14198568

申请日：2014-03-05

Applicant: Applied Materials, Inc.

Inventor： Zhigang Mao ,  Xiaoyi Chen ,  Amitabh Sabharwal ,  Ajay Kumar

IPC: H01L21/3065 ,  H01L21/3213 ,  G03F1/54 ,  G03F1/80 ,  H01L21/033 ,  H01L21/67 ,  G03F1/00 ,  C23F4/00 ,  H01L21/311

CPC classification number: H01L21/0338 ,  C23F4/00 ,  G03F1/00 ,  G03F1/24 ,  G03F1/54 ,  G03F1/80 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/31122 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/67069

Abstract: Embodiments of the present invention provides methods to etching a mask layer, e.g., an absorber layer, disposed in a film stack for manufacturing a photomask in EUV applications and phase shift and binary photomask applications. In one embodiment, a method of etching an absorber layer disposed on a photomask includes transferring a film stack into an etching chamber, the film stack having a chromium containing layer partially exposed through a patterned photoresist layer, providing an etching gas mixture including Cl2, O2 and at least one hydrocarbon gas in to a processing chamber, wherein the Cl2 and O2 is supplied at a Cl2:O2 ratio greater than about 9, supplying a RF source power to form a plasma from the etching gas mixture, and etching the chromium containing layer through the patterned photoresist layer in the presence of the plasma.

Abstract translation: 本发明的实施例提供了在EUV应用和相移和二进制光掩模应用中蚀刻设置在膜堆叠中用于制造光掩模的掩模层（例如吸收层）的方法。 在一个实施例中，蚀刻设置在光掩模上的吸收层的方法包括将膜堆叠转移到蚀刻室中，所述膜堆叠具有通过图案化的光致抗蚀剂层部分暴露的含铬层，提供包括Cl 2，O 2的蚀刻气体混合物 和至少一种烃气体输送到处理室中，其中Cl 2和O 2以大于约9的Cl 2：O 2比供应，提供RF源功率以从蚀刻气体混合物形成等离子体，并且蚀刻含铬 在等离子体的存在下通过图案化的光致抗蚀剂层。

公开(公告)号：US20160049313A1

公开(公告)日：2016-02-18

申请号：US14458220

申请日：2014-08-12

Applicant: Applied Materials, Inc.

Inventor： PRABHAT KUMAR ,  Wei-Sheng Lei ,  Martin S. Wohlert ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/322 ,  H01L21/67 ,  B01J3/00

CPC classification number: H01L21/3221 ,  H01L21/3081 ,  H01L21/67115 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67207 ,  H01L21/67393 ,  H01L21/67739 ,  H01L21/67748 ,  H01L21/78

Abstract: Embodiments of the invention include methods and apparatuses for outgassing a workpiece prior to a plasma processing operation. An embodiment of the invention may comprise transferring a workpiece having a mask to an outgassing station that has one or more heating elements. The workpiece may then be heated to an outgassing temperature that causes moisture from the mask layer to be outgassed. After outgassing the workpiece, the workpiece may be transferred to a plasma processing chamber. In an additional embodiment, one or more outgassing stations may be located within a process tool that has a factory interface, a load lock coupled to the factory interface, a transfer chamber coupled to the load lock, and a plasma processing chamber coupled to the transfer chamber. According to an embodiment, an outgassing station may be located within any of the components of the process tool.

Abstract translation: 本发明的实施例包括在等离子体处理操作之前使工件脱气的方法和装置。 本发明的实施例可以包括将具有掩模的工件传送到具有一个或多个加热元件的除气站。 然后可以将工件加热到使得来自掩模层的水分脱气的除气温度。 在对工件进行放气之后，可以将工件转移到等离子体处理室。 在另外的实施例中，一个或多个除气站可以位于处理工具内，该工具具有出厂界面，耦合到出厂界面的负载锁，耦合到负载锁的传送室以及耦合到传送的等离子体处理室 房间。 根据实施例，除气站可以位于处理工具的任何部件内。