公开(公告)号：US20240138147A1

公开(公告)日：2024-04-25

申请号：US18486576

申请日：2023-10-12

Applicant: Applied Materials, Inc.

Inventor： Jaesoo Ahn ,  Jose Alexandro Romero ,  Kunal Bhatnagar ,  Mahendra Pakala

IPC: H10B43/20 ,  H01L21/02

CPC classification number: H10B43/20 ,  H01L21/0228 ,  H10B43/35

Abstract: A method includes obtaining a base structure of a three-dimensional (3D) memory device, forming, on the base structure, a blocking layer including a high-k dielectric material, and forming, on the blocking layer, a wordline for the 3D memory device including molybdenum using an atomic layer deposition (ALD) process.

公开(公告)号：US20230102558A1

公开(公告)日：2023-03-30

申请号：US17487596

申请日：2021-09-28

Applicant: Applied Materials, Inc.

Inventor： Arvind Kumar ,  Mahendra Pakala ,  Ellie Y. Yieh ,  John Tolle ,  Thomas Kirschenheiter ,  Anchuan Wang ,  Zihui Li

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66

Abstract: Methods of reducing wafer bowing in 3D DRAM devices are described using a 3-color process. A plurality of film stacks are formed on a substrate surface, each of the film stacks comprises two doped SiGe layers having different dopant amounts and/or Si:Ge ratios and a doped silicon layer. 3D DRAM devices are also described.

公开(公告)号：US11552244B2

公开(公告)日：2023-01-10

申请号：US17193966

申请日：2021-03-05

Applicant: Applied Materials, Inc.

Inventor： Lin Xue ,  Chi Hong Ching ,  Rongjun Wang ,  Mahendra Pakala

IPC: H01L29/82 ,  H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Embodiments of magnetic tunnel junction (MTJ) structures discussed herein employ seed layers of one or more layer of chromium (Cr), NiCr, NiFeCr, RuCr, IrCr, or CoCr, or combinations thereof. These seed layers are used in combination with one or more pinning layers, a first pinning layer in contact with the seed layer can contain a single layer of cobalt, or can contain cobalt in combination with bilayers of cobalt and platinum (Pt), iridium (Ir), nickel (Ni), or palladium (Pd), The second pinning layer can be the same composition and configuration as the first, or can be of a different composition or configuration. The MTJ stacks discussed herein maintain desirable magnetic properties subsequent to high temperature annealing.

公开(公告)号：US11522126B2

公开(公告)日：2022-12-06

申请号：US16601250

申请日：2019-10-14

Applicant: Applied Materials, Inc.

Inventor： Lin Xue ,  Jaesoo Ahn ,  Sahil Patel ,  Chando Park ,  Mahendra Pakala

IPC: H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  G11B5/39 ,  H01L43/10 ,  H01L27/22 ,  H01L43/02

Abstract: A film stack for a magnetic tunnel comprises a substrate, a magnetic reference layer disposed over the substrate, and a tunnel barrier layer disposed over the magnetic reference layer. The film stack further comprises a magnetic storage layer disposed over the tunnel barrier layer, and a capping layer disposed over the magnetic storage layer. Further, the film stack comprises at least one protection layer disposed between the magnetic reference layer and the tunnel barrier layer and disposed between the magnetic storage layer and the capping layer. Additionally, a material forming the at least one protection layer differs from at least one of a material forming the magnetic reference layer and a material forming the magnetic storage layer.

公开(公告)号：US10923652B2

公开(公告)日：2021-02-16

申请号：US16448709

申请日：2019-06-21

Applicant: Applied Materials, Inc.

Inventor： Lin Xue ,  Chando Park ,  Chi Hong Ching ,  Jaesoo Ahn ,  Mahendra Pakala

IPC: H01L43/12 ,  H01L43/02 ,  G11C11/16 ,  C23C14/54 ,  H01F10/32 ,  H01L43/10 ,  H01F41/32 ,  C23C14/06 ,  H01L21/67 ,  H01F10/13

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate for MRAM applications. In one embodiment, a magnetic tunnel junction (MTJ) device structure includes a junction structure disposed on a substrate, the junction structure comprising a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer, a dielectric capping layer disposed on the junction structure, a metal capping layer disposed on the junction structure, and a top buffer layer disposed on the metal capping layer.

公开(公告)号：US10756259B2

公开(公告)日：2020-08-25

申请号：US16290621

申请日：2019-03-01

Applicant: Applied Materials, Inc.

Inventor： Jaesoo Ahn ,  Chando Park ,  Hsin-wei Tseng ,  Lin Xue ,  Mahendra Pakala

IPC: H01L27/00 ,  H01L43/00 ,  H01L43/12 ,  H01L43/02 ,  H01L43/10 ,  H01L27/22

Abstract: The bottom-pinned spin-orbit torque (SOT) MRAM devices are fabricated to form high quality interfaces between layers including the spin-orbit torque (SOT) layer and the free layer of the magnetic tunnel junction (MTJ) by forming those layers under vacuum, without breaking vacuum in between formation of the layers. An encapsulation layer is used as an etch stop and to protect the free layer. The encapsulation layer is etched back prior to the deposition of a metal layer. The metal layer forms a plurality of metal lines that are electrically connected to two or more sides of the SOT layer and are electrically coupled to the SOT layer to transfer current through the SOT layer. The metal lines are not in contact with a top surface of the SOT layer which has a dielectric layer disposed thereon.

公开(公告)号：US10586914B2

公开(公告)日：2020-03-10

申请号：US15712185

申请日：2017-09-22

Applicant: Applied Materials, Inc.

Inventor： Lin Xue ,  Sajjad Amin Hassan ,  Mahendra Pakala ,  Jaesoo Ahn

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

Abstract: A process sequence is provided to provide an ultra-smooth (0.2 nm or less) bottom electrode surface for depositing magnetic tunnel junctions thereon. In one embodiment, the sequence includes forming a bottom electrode pad through bulk layer deposition followed by patterning and etching. Oxide is then deposited over the formed bottom electrode pads and polished back to expose the bottom electrode pads. A bottom electrode buff layer is then deposited thereover following a pre-clean operation. The bottom electrode buff layer is then exposed to a CMP process to improve surface roughness. An MTJ deposition is then performed over the bottom electrode buff layer.

公开(公告)号：US11764058B2

公开(公告)日：2023-09-19

申请号：US17487596

申请日：2021-09-28

Applicant: Applied Materials, Inc.

Inventor： Arvind Kumar ,  Mahendra Pakala ,  Ellie Y. Yieh ,  John Tolle ,  Thomas Kirschenheiter ,  Anchuan Wang ,  Zihui Li

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L21/306 ,  H10B12/00

CPC classification number: H01L21/02532 ,  H01L21/0259 ,  H01L21/0262 ,  H01L21/02579 ,  H01L21/30604 ,  H01L29/0665 ,  H01L29/66742 ,  H01L29/78696 ,  H10B12/05 ,  H10B12/30

Abstract: Methods of reducing wafer bowing in 3D DRAM devices are described using a 3-color process. A plurality of film stacks are formed on a substrate surface, each of the film stacks comprises two doped SiGe layers having different dopant amounts and/or Si:Ge ratios and a doped silicon layer. 3D DRAM devices are also described.

公开(公告)号：US11456301B2

公开(公告)日：2022-09-27

申请号：US16931154

申请日：2020-07-16

Applicant: Applied Materials, Inc.

Inventor： Arvind Kumar ,  Mahendra Pakala ,  Sanjeev Manhas ,  Satendra Kumar Gautam

IPC: H01L27/108 ,  H01L21/28 ,  H01L29/49

Abstract: Embodiments of the present disclosure generally relate to a storage device. More specifically, embodiments described herein generally relate to a dynamic random-access memory and the method of making thereof. In one embodiment, a cell array includes at least an active region and a field region adjacent to the active region. The active region includes at least one trench, a dielectric layer disposed in the trench, a first conformal layer disposed on the dielectric layer, and a conductive material disposed on the first conformal layer. The field region includes a trench, a dielectric layer disposed in the trench, a second conformal layer disposed on the dielectric layer, and a conductive material disposed on the second conformal layer. The second conformal layer has a different composition than the first conformal layer.

公开(公告)号：US11374170B2

公开(公告)日：2022-06-28

申请号：US16141470

申请日：2018-09-25

Applicant: Applied Materials, Inc.

Inventor： Lin Xue ,  Jaesoo Ahn ,  Hsin-wei Tseng ,  Mahendra Pakala

IPC: H01L43/12 ,  H01L43/10

Abstract: Embodiments of the disclosure relate to methods for fabricating structures used in memory devices. More specifically, embodiments of the disclosure relate to methods for fabricating MTJ structures in memory devices. In one embodiment, the method includes forming a MTJ structure, depositing a encapsulating layer on a top and sides of the MTJ structure, depositing a dielectric material on the encapsulating layer, removing the dielectric material and the encapsulating layer disposed on the top of the MTJ structure by a chemical mechanical planarization (CMP) process to expose the top of the MTJ structure, and depositing a contact layer on the MTJ structure. The method utilizes a CMP process to expose the top of the MTJ structure instead of an etching process, which avoids damaging the MTJ structure and leads to improved electrical contact between the MTJ structure and the contact layer.