公开(公告)号：US20240363337A1

公开(公告)日：2024-10-31

申请号：US18139699

申请日：2023-04-26

Applicant: Applied Materials, Inc.

Inventor： Muthukumar Kaliappan ,  Bo Xie ,  Shanshan Yao ,  Li-Qun Xia ,  Michael Haverty ,  Rui Lu ,  Xiaobo Li ,  Chi-I Lang ,  Shankar Venkataraman

IPC: H01L21/02 ,  C23C16/32 ,  C23C16/455 ,  C23C16/56

CPC classification number: H01L21/02167 ,  C23C16/325 ,  C23C16/45542 ,  C23C16/45553 ,  C23C16/45565 ,  C23C16/56 ,  H01L21/02211 ,  H01L21/02274

Abstract: Semiconductor processing methods are described for forming low-κ dielectric materials. The methods may include providing deposition precursors to a processing region of a semiconductor processing chamber. The deposition precursors may include a silicon-carbon-and-hydrogen-containing precursor. A substrate may be disposed within the processing region. The methods may include forming plasma effluents of the deposition precursors. The methods may include depositing a layer of silicon-containing material on the substrate. The layer of silicon-containing material may be characterized by a dielectric constant of less than or about 4.0.

公开(公告)号：US20240355675A1

公开(公告)日：2024-10-24

申请号：US18630177

申请日：2024-04-09

Applicant: Applied Materials, Inc.

Inventor： Muthukumar Kaliappan ,  Yong Jin Kim ,  Carmen Leal Cervantes ,  Bhaskar Jyoti Bhuyan ,  Xiangjin Xie ,  Michael Haverty ,  Kevin Kashefi ,  Mark Saly ,  Aaron Dangerfield ,  Jesus Candelario Mendoza-Gutierrez

IPC: H01L21/768

CPC classification number: H01L21/76846 ,  H01L21/76879

Abstract: Methods of forming semiconductor devices by enhancing selective deposition are described. In some embodiments, a blocking layer is deposited on a metal surface before deposition of a barrier layer. The methods include exposing a substrate with a metal surface, a dielectric surface and an aluminum oxide surface or an aluminum nitride surface to a blocking molecule, such as a boron-containing compound, to form the blocking layer selectively on the metal surface over the dielectric surface and one of the aluminum oxide surface or the aluminum nitride surface.

公开(公告)号：US11702733B2

公开(公告)日：2023-07-18

申请号：US17315223

申请日：2021-05-07

Applicant: Applied Materials, Inc.

Inventor： Lakmal C. Kalutarage ,  Bhaskar Jyoti Bhuyan ,  Aaron Dangerfield ,  Feng Q. Liu ,  Mark Saly ,  Michael Haverty ,  Muthukumar Kaliappan

IPC: C23C16/04 ,  C23C16/02 ,  H01L21/02 ,  H01L21/32 ,  C23C16/56

CPC classification number: C23C16/042 ,  C23C16/0272 ,  C23C16/56 ,  H01L21/0228 ,  H01L21/02172 ,  H01L21/32 ,  H01L21/0217 ,  H01L21/02211

Abstract: Methods of selectively depositing blocking layers on conductive surfaces over dielectric surfaces are described. In some embodiments, a 4-8 membered substituted heterocycle is exposed to a substrate to selectively form a blocking layer. In some embodiments, a layer is selectively deposited on the dielectric surface after the blocking layer is formed. In some embodiments, the blocking layer is removed.

公开(公告)号：US20230268414A1

公开(公告)日：2023-08-24

申请号：US17863647

申请日：2022-07-13

Applicant: Applied Materials, Inc.

Inventor： Michael Haverty ,  Avgerinos V. Gelatos ,  Gaurav Thareja ,  Seshadri Ganguli

IPC: H01L29/45 ,  H01L21/285

CPC classification number: H01L29/456 ,  H01L21/28518

Abstract: Embodiments of the disclosure provide methods and electronic devices comprising a work function layer comprising a material that forms a weak silicide. The electronic devices comprise a silicon layer with the work function layer thereon and a metal contact on the work function layer.

公开(公告)号：US20230268399A1

公开(公告)日：2023-08-24

申请号：US17863644

申请日：2022-07-13

Applicant: Applied Materials, Inc.

Inventor： Michael Haverty ,  Avgerinos V. Gelatos ,  Muthukumar Kaliappan

IPC: H01L29/40 ,  H01L29/49

CPC classification number: H01L29/401 ,  H01L29/495 ,  H01L29/41791

Abstract: Embodiments of the disclosure provide methods and electronic devices comprising a work function layer comprising a material that does not form a silicide. The electronic devices comprise a silicon layer with the work function layer thereon and a metal contact on the work function layer.

公开(公告)号：US11658025B2

公开(公告)日：2023-05-23

申请号：US17151240

申请日：2021-01-18

Applicant: Applied Materials, Inc. ,  National University of Singapore

Inventor： Chandan Kr Barik ,  Michael Haverty ,  Muthukumar Kaliappan ,  Cong Trinh ,  Bhaskar Jyoti Bhuyan ,  John Sudijono ,  Anil Kumar Tummanapelli ,  Richard Ming Wah Wong ,  Yingqian Chen

IPC: H01L21/02 ,  C23C16/34 ,  C23C16/44 ,  C23C16/455

CPC classification number: H01L21/02211 ,  C23C16/345 ,  C23C16/4408 ,  C23C16/45553 ,  H01L21/0217 ,  H01L21/0228

Abstract: Chalcogen silane precursors are described. Methods for depositing a silicon nitride (SixNy) film on a substrate are described. The substrate is exposed to the chalcogen silane and a reactant to deposit the silicon nitride (SixNy) film. The exposures can be sequential or simultaneous. The chalcogen silane may be substantially free of halogen. The chalcogen may be selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te).

公开(公告)号：US11626288B2

公开(公告)日：2023-04-11

申请号：US17389772

申请日：2021-07-30

Applicant: Applied Materials, Inc.

Inventor： Raymond Hung ,  Mehul Naik ,  Michael Haverty

IPC: H01L21/285 ,  H01L29/45 ,  H01L29/47 ,  H01L29/40 ,  H01L29/417

Abstract: Methods for reducing interface resistance of semiconductor devices leverage dual work function metal silicide. In some embodiments, a method may comprise selectively depositing a metal silicide layer on an Epi surface and adjusting a metal-to-silicon ratio of the metal silicide layer during deposition to alter a work function of the metal silicide layer based on whether the Epi surface is a P type Epi surface or an N type Epi surface to achieve a Schottky barrier height of less than 0.5 eV. The work function for a P type Epi surface may be adjusted to a value of approximately 5.0 eV and the work function for an N type Epi surface may be adjusted to a value of approximately 3.8 eV. The deposition of the metal silicide layer on the Epi surface may be performed prior to deposition of a contact etch stop layer and an activation anneal.

公开(公告)号：US12142477B2

公开(公告)日：2024-11-12

申请号：US18134802

申请日：2023-04-14

Applicant: Applied Materials, Inc. ,  National University of Singapore

Inventor： Chandan Kr Barik ,  Michael Haverty ,  Muthukumar Kaliappan ,  Cong Trinh ,  Bhaskar Jyoti Bhuyan ,  John Sudijono ,  Anil Kumar Tummanapelli ,  Richard Ming Wah Wong ,  Yingqian Chen

IPC: H01L21/02 ,  C23C16/34 ,  C23C16/44 ,  C23C16/455

Abstract: Chalcogen silane precursors are described. Methods for depositing a silicon nitride (SixNy) film on a substrate are described. The substrate is exposed to the chalcogen silane and a reactant to deposit the silicon nitride (SixNy) film. The exposures can be sequential or simultaneous. The chalcogen silane may be substantially free of halogen. The chalcogen may be selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te).

公开(公告)号：US12141688B2

公开(公告)日：2024-11-12

申请号：US17380318

申请日：2021-07-20

Applicant: Applied Materials, Inc.

Inventor： Milan Pesic ,  Shruba Gangopadhyay ,  Muthukumar Kaliappan ,  Michael Haverty

IPC: G06N3/065 ,  G11C11/54 ,  G11C13/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

Abstract: A crested barrier memory device may include a first electrode, a first self-rectifying layer, and a combined barrier and active layer. The first self-rectifying layer may be between the first electrode and the active layer. A conduction band offset between the first self-rectifying layer and the combined barrier and active layer may be greater than approximately 1.5 eV. A valence band offset between the first self-rectifying layer and the combined barrier and active layer may be less than approximately −0.5 eV. The device may also include a second electrode. The active layer may be between the first self-rectifying layer and the second electrode.

公开(公告)号：US20240297073A1

公开(公告)日：2024-09-05

申请号：US18117203

申请日：2023-03-03

Applicant: Applied Materials, Inc.

Inventor： Muthukumar Kaliappan ,  Bhaskar Jyoti Bhuyan ,  Yong Jin Kim ,  Carmen Leal Cervantes ,  Xiangjin Xie ,  Jesus Candelario Mendoza-Gutierrez ,  Aaron Dangerfield ,  Michael Haverty ,  Mark Saly ,  Kevin Kashefi

IPC: H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/76831 ,  H01L21/76877

Abstract: Methods of forming semiconductor devices by enhancing selective deposition are described. In some embodiments, a blocking layer is deposited on a metal surface before deposition of a barrier layer. The methods include exposing a substrate with a metal surface, a dielectric surface and an aluminum oxide surface or an aluminum nitride surface to a blocking molecule to form the blocking layer selectively on the metal surface over the dielectric surface and one of the aluminum oxide surface or the aluminum nitride surface.