公开(公告)号：US12178146B2

公开(公告)日：2024-12-24

申请号：US18190971

申请日：2023-03-28

Applicant: Applied Materials, Inc.

Inventor： Deepak Kamalanathan ,  Archana Kumar ,  Siddarth Krishnan

IPC: H10N70/20 ,  H10N70/00

Abstract: Exemplary semiconductor structures for neuromorphic applications may include a first layer overlying a substrate material. The first layer may be or include a first oxide material. The structures may include a second layer disposed adjacent the first layer. The second layer may be or include a second oxide material. The structures may also include an electrode material deposited overlying the second layer.

公开(公告)号：US20240282813A1

公开(公告)日：2024-08-22

申请号：US18171119

申请日：2023-02-17

Applicant: Applied Materials, Inc.

Inventor： Amirhasan Nourbakhsh ,  Raman Gaire ,  Roger Quon ,  Siddarth Krishnan

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/3065 ,  H01L29/0649 ,  H01L29/66712 ,  H01L29/7802

Abstract: A super junction device with an increased manufacturing throughput may be formed by forming narrow trenches lined with a P-type liner and rapidly filled with a passive fill material. Instead of etching trenches with aspect ratio large enough to reliably fill with doped P-type material, the aspect ratio of the trench may be reduced to shrink the size of the device. This smaller trench may then be lined with a relatively thin (e.g., about 1 μm to about 2 μm) P-type liner instead of completely filling the trench with P-type material. Inside the P-type liner, the trench may then be filled with a passive fill material. Filling the trench with the passive fill material may be carried out in a matter of minutes at relatively high temperatures, thereby likely causing a void or seam to form within the passive fill material. However, because the passive fill material does not affect the operation of the device, this type of defect can exist in the device.

公开(公告)号：US11837285B2

公开(公告)日：2023-12-05

申请号：US17408429

申请日：2021-08-22

Applicant: Applied Materials, Inc.

Inventor： Christophe J. Chevallier ,  Siddarth Krishnan

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/16

CPC classification number: G11C13/0023 ,  G11C11/1653 ,  G11C11/1675 ,  G11C13/0069 ,  G11C2213/79

Abstract: A method of correcting bias temperature instability in memory arrays may include applying a first bias to a memory cell, where the memory cell may include a memory element and a select element, and the first bias may causes a value to be stored in the memory element. The first bias causes a bias temperature instability (BTI) associated with the memory cell to increase. The method may also include applying a second bias to the memory cell, where the second bias may have a polarity that is opposite of the first bias, and the value stored in the memory element remains in the memory element after the second bias is applied. The second bias may also cause the BTI associated with the memory cell to decrease while maintaining any value stored in the memory cell.

公开(公告)号：US11705490B2

公开(公告)日：2023-07-18

申请号：US17169916

申请日：2021-02-08

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  El Mehdi Bazizi ,  Siddarth Krishnan ,  Xing Chen ,  Lan Yu ,  Tyler Sherwood

IPC: H01L21/02 ,  H01L29/36 ,  H01L29/872 ,  H01L29/66 ,  H01L21/285 ,  H01L21/3065 ,  H01L21/265

CPC classification number: H01L29/36 ,  H01L21/02164 ,  H01L21/26513 ,  H01L21/28537 ,  H01L21/3065 ,  H01L29/66143 ,  H01L29/872

Abstract: Exemplary methods of forming a semiconductor structure may include forming a doped silicon layer on a semiconductor substrate. A level of doping may be increased at an increasing distance from the semiconductor substrate. The methods may include etching the doped silicon layer to define a trench extending to the semiconductor substrate. The doped silicon layer may define a sloping sidewall of the trench. The trench may be characterized by a depth of greater than or about 30 μm. The methods may include lining the trench with a first oxide material. The methods may include depositing a second oxide material within the trench. The methods may include forming a contact to produce a power device.

公开(公告)号：US20230015781A1

公开(公告)日：2023-01-19

申请号：US17376504

申请日：2021-07-15

Applicant: Applied Materials, Inc.

Inventor： Ria Someshwar ,  Seshadri Ganguli ,  Lan Yu ,  Siddarth Krishnan ,  Srinivas Gandikota ,  Jacqueline S. Wrench ,  Yixiong Yang

IPC: H01L29/45 ,  H01L29/40 ,  H01L21/285 ,  H01L21/324

Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.

公开(公告)号：US11362275B2

公开(公告)日：2022-06-14

申请号：US16855122

申请日：2020-04-22

Applicant: Applied Materials, Inc.

Inventor： Nicolas Louis Gabriel Breil ,  Siddarth Krishnan ,  Shashank Sharma ,  Ria Someshwar ,  Kai Ng ,  Deepak Kamalanathan

IPC: H01L45/00 ,  H01L27/24

Abstract: Exemplary methods of forming a memory structure may include forming a layer of a transition-metal-and-oxygen-containing material overlying a substrate. The substrate may include a first electrode material. The methods may include annealing the transition-metal-and-oxygen-containing material at a temperature greater than or about 500° C. The annealing may occur for a time period less than or about one second. The methods may also include, subsequent the annealing, forming a layer of a second electrode material over the transition-metal-and-oxygen-containing material.

公开(公告)号：US20240258375A1

公开(公告)日：2024-08-01

申请号：US18160949

申请日：2023-01-27

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  Pratik B. Vyas ,  El Mehdi Bazizi ,  Stephen Weeks ,  Ludovico Megalini ,  Siddarth Krishnan

IPC: H01L29/10 ,  H01L21/04 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/105 ,  H01L21/046 ,  H01L29/1608 ,  H01L29/66068

Abstract: A silicon carbide transistor may be formed with a channel that includes a p-doped region between n-doped source and drain regions. A counter-doped region may be formed at the top of the channel directly underneath the gate oxide. Instead of using the conventional doping levels for the p-doped region, the doping concentration may be increase to be greater than about 1e18 cm3. The transistor may also include pocket regions on one or both sides of the channel. The pocket regions may be formed in the counter-doped region and may extend up to the gate oxide. These improvements individually and/or in combination may increase the current in the channel of the transistor without significantly increasing the threshold voltage beyond acceptable operating limits.

公开(公告)号：US20240154018A1

公开(公告)日：2024-05-09

申请号：US18411693

申请日：2024-01-12

Applicant: Applied Materials, Inc.

Inventor： Ria Someshwar ,  Seshadri Ganguli ,  Lan Yu ,  Siddarth Krishnan ,  Srinivas Gandikota ,  Jacqueline S. Wrench ,  Yixiong Yang

IPC: H01L29/45 ,  H01L21/285 ,  H01L21/324 ,  H01L21/8238 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/456 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/401 ,  H01L29/45 ,  H01L29/665

Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.

公开(公告)号：US11790989B2

公开(公告)日：2023-10-17

申请号：US17329008

申请日：2021-05-24

Applicant: Applied Materials, Inc.

Inventor： Deepak Kamalanathan ,  Siddarth Krishnan ,  Archana Kumar ,  Fuxi Cai ,  Federico Nardi

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0097 ,  G11C13/004 ,  G11C13/0038 ,  G11C13/0069

Abstract: A method for setting memory elements in a plurality of states includes applying a set signal to a memory element to transition the memory element from a low-current state to a high-current state; applying a partial reset signal to the memory element to transition the memory element from the high-current state to a state between the high-current state and the low-current state; determining whether the state corresponds to a predetermined state; and applying one or more additional partial reset signals to the memory element until the state corresponds to the predetermined current state. The memory element may be coupled in series with a transistor, and a voltage control circuit may apply voltages to the transistor to set and partially reset the memory element.

公开(公告)号：US11605741B2

公开(公告)日：2023-03-14

申请号：US17102148

申请日：2020-11-23

Applicant: Applied Materials, Inc.

Inventor： Joshua S. Holt ,  Lan Yu ,  Tyler Sherwood ,  Archana Kumar ,  Nicolas Louis Gabriel Breil ,  Siddarth Krishnan

IPC: H01L29/872 ,  H01L21/28 ,  H01L29/45 ,  H01L29/861 ,  H01L29/66 ,  H01L29/47

Abstract: Exemplary methods of forming a semiconductor structure may include forming a layer of metal on a semiconductor substrate. The layer of metal may extend along a first surface of the semiconductor substrate. The semiconductor substrate may be or include silicon. The methods may include performing an anneal to produce a metal silicide. The methods may include implanting ions in the metal silicide to increase a barrier height over 0.65 V.